| 6693962c | 13-Mar-2015 |
Varun Wadekar <vwadekar@nvidia.com> |
Open/Close TA sessions, send commands/events to TAs
This patch adds support to open/close secure sessions with Trusted Apps and later send commands/events. Modify TLK_NUM_FID to indicate the total n
Open/Close TA sessions, send commands/events to TAs
This patch adds support to open/close secure sessions with Trusted Apps and later send commands/events. Modify TLK_NUM_FID to indicate the total number of FIDs available to the NS world.
Change-Id: I3f1153dfa5510bd44fc25f1fee85cae475b1abf1 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
show more ...
|
| f9d25054 | 13-Mar-2015 |
Varun Wadekar <vwadekar@nvidia.com> |
Preempt/Resume standard function ID calls
This patch allows servicing of the non-secure world IRQs when the CPU is in the secure world. Once the interrupt is handled, the non-secure world issues the
Preempt/Resume standard function ID calls
This patch allows servicing of the non-secure world IRQs when the CPU is in the secure world. Once the interrupt is handled, the non-secure world issues the Resume FID to allow the secure payload complete the preempted standard FID.
Change-Id: Ia52c41adf45014ab51d8447bed6605ca2f935587 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
show more ...
|
| 77199df7 | 13-Mar-2015 |
Varun Wadekar <vwadekar@nvidia.com> |
Register NS shared memory for SP's activity logs and TA sessions
This patch registers NS memory buffer with the secure payload using two different functions IDs - REGISTER_LOGBUF, REGISTER_REQBUF.
Register NS shared memory for SP's activity logs and TA sessions
This patch registers NS memory buffer with the secure payload using two different functions IDs - REGISTER_LOGBUF, REGISTER_REQBUF.
a. The SP uses the log-buffer to store its activity logs, in a pre-decided format. This helps in debugging secure payload's issues. b. The SP uses the req-buffer to get the parameters required by sessions with Trusted Applications.
Change-Id: I6b0247cf7790524132ee0da24f1f35b1fccec5d5 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
show more ...
|
| 399fb08f | 20-May-2014 |
Andrew Thoelke <andrew.thoelke@arm.com> |
Use a vector table for TSP entrypoints
The TSP has a number of entrypoints used by the TSP on different occasions. These were provided to the TSPD as a table of function pointers, and required the T
Use a vector table for TSP entrypoints
The TSP has a number of entrypoints used by the TSP on different occasions. These were provided to the TSPD as a table of function pointers, and required the TSPD to read the entry in the table, which is in TSP memory, in order to program the exception return address.
Ideally, the TSPD has no access to the TSP memory.
This patch changes the table of function pointers into a vector table of single instruction entrypoints. This allows the TSPD to calculate the entrypoint address instead of read it.
Fixes ARM-software/tf-issues#160
Change-Id: Iec6e055d537ade78a45799fbc6f43765a4725ad3
show more ...
|
| 6cf89021 | 09-May-2014 |
Achin Gupta <achin.gupta@arm.com> |
Add support for synchronous FIQ handling in TSP
This patch adds support in the TSP for handling S-EL1 interrupts handed over by the TSPD. It includes GIC support in its platform port, updates variou
Add support for synchronous FIQ handling in TSP
This patch adds support in the TSP for handling S-EL1 interrupts handed over by the TSPD. It includes GIC support in its platform port, updates various statistics related to FIQ handling, exports an entry point that the TSPD can use to hand over interrupts and defines the handover protocol w.r.t what context is the TSP expected to preserve and the state in which the entry point is invoked by the TSPD.
Change-Id: I93b22e5a8133400e4da366f5fc862f871038df39
show more ...
|