1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <cci.h> 11 #include <console.h> 12 #include <debug.h> 13 #include <errno.h> 14 #include <generic_delay_timer.h> 15 #include <gicv2.h> 16 #include <hi3660.h> 17 #include <hisi_ipc.h> 18 #include <interrupt_mgmt.h> 19 #include <interrupt_props.h> 20 #include <platform.h> 21 #include <platform_def.h> 22 23 #include "hikey960_def.h" 24 #include "hikey960_private.h" 25 26 /* 27 * The next 2 constants identify the extents of the code & RO data region. 28 * These addresses are used by the MMU setup code and therefore they must be 29 * page-aligned. It is the responsibility of the linker script to ensure that 30 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. 31 */ 32 #define BL31_RO_BASE (unsigned long)(&__RO_START__) 33 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 34 35 /* 36 * The next 2 constants identify the extents of the coherent memory region. 37 * These addresses are used by the MMU setup code and therefore they must be 38 * page-aligned. It is the responsibility of the linker script to ensure that 39 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 40 * page-aligned addresses. 41 */ 42 #define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 43 #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 44 45 static entry_point_info_t bl32_ep_info; 46 static entry_point_info_t bl33_ep_info; 47 48 /****************************************************************************** 49 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 50 * interrupts. 51 *****************************************************************************/ 52 static const interrupt_prop_t g0_interrupt_props[] = { 53 INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, 54 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 55 INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, 56 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 57 }; 58 59 const gicv2_driver_data_t hikey960_gic_data = { 60 .gicd_base = GICD_REG_BASE, 61 .gicc_base = GICC_REG_BASE, 62 .interrupt_props = g0_interrupt_props, 63 .interrupt_props_num = ARRAY_SIZE(g0_interrupt_props), 64 }; 65 66 static const int cci_map[] = { 67 CCI400_SL_IFACE3_CLUSTER_IX, 68 CCI400_SL_IFACE4_CLUSTER_IX 69 }; 70 71 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 72 { 73 entry_point_info_t *next_image_info; 74 75 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 76 77 /* None of the images on this platform can have 0x0 as the entrypoint */ 78 if (next_image_info->pc) 79 return next_image_info; 80 return NULL; 81 } 82 83 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 84 u_register_t arg2, u_register_t arg3) 85 { 86 unsigned int id, uart_base; 87 void *from_bl2; 88 89 from_bl2 = (void *) arg0; 90 91 generic_delay_timer_init(); 92 hikey960_read_boardid(&id); 93 if (id == 5300) 94 uart_base = PL011_UART5_BASE; 95 else 96 uart_base = PL011_UART6_BASE; 97 98 /* Initialize the console to provide early debug support */ 99 console_init(uart_base, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE); 100 101 /* Initialize CCI driver */ 102 cci_init(CCI400_REG_BASE, cci_map, ARRAY_SIZE(cci_map)); 103 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); 104 105 /* 106 * Check params passed from BL2 should not be NULL, 107 */ 108 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 109 assert(params_from_bl2 != NULL); 110 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 111 assert(params_from_bl2->h.version >= VERSION_2); 112 113 bl_params_node_t *bl_params = params_from_bl2->head; 114 115 /* 116 * Copy BL33 and BL32 (if present), entry point information. 117 * They are stored in Secure RAM, in BL2's address space. 118 */ 119 while (bl_params) { 120 if (bl_params->image_id == BL32_IMAGE_ID) 121 bl32_ep_info = *bl_params->ep_info; 122 123 if (bl_params->image_id == BL33_IMAGE_ID) 124 bl33_ep_info = *bl_params->ep_info; 125 126 bl_params = bl_params->next_params_info; 127 } 128 129 if (bl33_ep_info.pc == 0) 130 panic(); 131 } 132 133 void bl31_plat_arch_setup(void) 134 { 135 hikey960_init_mmu_el3(BL31_BASE, 136 BL31_LIMIT - BL31_BASE, 137 BL31_RO_BASE, 138 BL31_RO_LIMIT, 139 BL31_COHERENT_RAM_BASE, 140 BL31_COHERENT_RAM_LIMIT); 141 } 142 143 void bl31_platform_setup(void) 144 { 145 /* Initialize the GIC driver, cpu and distributor interfaces */ 146 gicv2_driver_init(&hikey960_gic_data); 147 gicv2_distif_init(); 148 gicv2_pcpu_distif_init(); 149 gicv2_cpuif_enable(); 150 151 hisi_ipc_init(); 152 } 153 154 #ifdef SPD_none 155 static uint64_t hikey_debug_fiq_handler(uint32_t id, 156 uint32_t flags, 157 void *handle, 158 void *cookie) 159 { 160 int intr, intr_raw; 161 162 /* Acknowledge interrupt */ 163 intr_raw = plat_ic_acknowledge_interrupt(); 164 intr = plat_ic_get_interrupt_id(intr_raw); 165 ERROR("Invalid interrupt: intr=%d\n", intr); 166 console_flush(); 167 panic(); 168 169 return 0; 170 } 171 #endif 172 173 void bl31_plat_runtime_setup(void) 174 { 175 #ifdef SPD_none 176 uint32_t flags; 177 int32_t rc; 178 179 flags = 0; 180 set_interrupt_rm_flag(flags, NON_SECURE); 181 rc = register_interrupt_type_handler(INTR_TYPE_S_EL1, 182 hikey_debug_fiq_handler, 183 flags); 184 if (rc != 0) 185 panic(); 186 #endif 187 } 188