1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bakery_lock.h> 10 #include <bl_common.h> 11 #include <context.h> 12 #include <context_mgmt.h> 13 #include <debug.h> 14 #include <denver.h> 15 #include <interrupt_mgmt.h> 16 #include <platform.h> 17 #include <tegra_def.h> 18 #include <tegra_private.h> 19 20 static DEFINE_BAKERY_LOCK(tegra_fiq_lock); 21 22 /******************************************************************************* 23 * Static variables 24 ******************************************************************************/ 25 static uint64_t ns_fiq_handler_addr; 26 static uint32_t fiq_handler_active; 27 static pcpu_fiq_state_t fiq_state[PLATFORM_CORE_COUNT]; 28 29 /******************************************************************************* 30 * Handler for FIQ interrupts 31 ******************************************************************************/ 32 static uint64_t tegra_fiq_interrupt_handler(uint32_t id, 33 uint32_t flags, 34 void *handle, 35 void *cookie) 36 { 37 cpu_context_t *ctx = cm_get_context(NON_SECURE); 38 el3_state_t *el3state_ctx = get_el3state_ctx(ctx); 39 uint32_t cpu = plat_my_core_pos(); 40 uint32_t irq; 41 42 bakery_lock_get(&tegra_fiq_lock); 43 44 /* 45 * The FIQ was generated when the execution was in the non-secure 46 * world. Save the context registers to start with. 47 */ 48 cm_el1_sysregs_context_save(NON_SECURE); 49 50 /* 51 * Save elr_el3 and spsr_el3 from the saved context, and overwrite 52 * the context with the NS fiq_handler_addr and SPSR value. 53 */ 54 fiq_state[cpu].elr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_ELR_EL3)); 55 fiq_state[cpu].spsr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_SPSR_EL3)); 56 57 /* 58 * Set the new ELR to continue execution in the NS world using the 59 * FIQ handler registered earlier. 60 */ 61 assert(ns_fiq_handler_addr); 62 write_ctx_reg((el3state_ctx), (uint32_t)(CTX_ELR_EL3), (ns_fiq_handler_addr)); 63 64 /* 65 * Mark this interrupt as complete to avoid a FIQ storm. 66 */ 67 irq = plat_ic_acknowledge_interrupt(); 68 if (irq < 1022U) { 69 plat_ic_end_of_interrupt(irq); 70 } 71 72 bakery_lock_release(&tegra_fiq_lock); 73 74 return 0; 75 } 76 77 /******************************************************************************* 78 * Setup handler for FIQ interrupts 79 ******************************************************************************/ 80 void tegra_fiq_handler_setup(void) 81 { 82 uint32_t flags; 83 int32_t rc; 84 85 /* return if already registered */ 86 if (fiq_handler_active == 0U) { 87 /* 88 * Register an interrupt handler for FIQ interrupts generated for 89 * NS interrupt sources 90 */ 91 flags = 0U; 92 set_interrupt_rm_flag((flags), (NON_SECURE)); 93 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 94 tegra_fiq_interrupt_handler, 95 flags); 96 if (rc != 0) { 97 panic(); 98 } 99 100 /* handler is now active */ 101 fiq_handler_active = 1; 102 } 103 } 104 105 /******************************************************************************* 106 * Validate and store NS world's entrypoint for FIQ interrupts 107 ******************************************************************************/ 108 void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint) 109 { 110 ns_fiq_handler_addr = entrypoint; 111 } 112 113 /******************************************************************************* 114 * Handler to return the NS EL1/EL0 CPU context 115 ******************************************************************************/ 116 int32_t tegra_fiq_get_intr_context(void) 117 { 118 cpu_context_t *ctx = cm_get_context(NON_SECURE); 119 gp_regs_t *gpregs_ctx = get_gpregs_ctx(ctx); 120 const el1_sys_regs_t *el1state_ctx = get_sysregs_ctx(ctx); 121 uint32_t cpu = plat_my_core_pos(); 122 uint64_t val; 123 124 /* 125 * We store the ELR_EL3, SPSR_EL3, SP_EL0 and SP_EL1 registers so 126 * that el3_exit() sends these values back to the NS world. 127 */ 128 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X0), (fiq_state[cpu].elr_el3)); 129 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X1), (fiq_state[cpu].spsr_el3)); 130 131 val = read_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_SP_EL0)); 132 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X2), (val)); 133 134 val = read_ctx_reg((el1state_ctx), (uint32_t)(CTX_SP_EL1)); 135 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X3), (val)); 136 137 return 0; 138 } 139