1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CSS_DEF_H 8 #define CSS_DEF_H 9 10 #include <common/interrupt_props.h> 11 #include <drivers/arm/gic_common.h> 12 #include <drivers/arm/tzc400.h> 13 14 #include <arm_def.h> 15 16 /************************************************************************* 17 * Definitions common to all ARM Compute SubSystems (CSS) 18 *************************************************************************/ 19 #define NSROM_BASE 0x1f000000 20 #define NSROM_SIZE 0x00001000 21 22 /* Following covers CSS Peripherals excluding NSROM and NSRAM */ 23 #define CSS_DEVICE_BASE 0x20000000 24 #define CSS_DEVICE_SIZE 0x0e000000 25 26 /* System Security Control Registers */ 27 #define SSC_REG_BASE 0x2a420000 28 #define SSC_GPRETN (SSC_REG_BASE + 0x030) 29 30 /* System ID Registers Unit */ 31 #define SID_REG_BASE 0x2a4a0000 32 #define SID_SYSTEM_ID_OFFSET 0x40 33 #define SID_SYSTEM_CFG_OFFSET 0x70 34 35 /* The slave_bootsecure controls access to GPU, DMC and CS. */ 36 #define CSS_NIC400_SLAVE_BOOTSECURE 8 37 38 /* Interrupt handling constants */ 39 #define CSS_IRQ_MHU 69 40 #define CSS_IRQ_GPU_SMMU_0 71 41 #define CSS_IRQ_TZC 80 42 #define CSS_IRQ_TZ_WDOG 86 43 #define CSS_IRQ_SEC_SYS_TIMER 91 44 45 /* MHU register offsets */ 46 #define MHU_CPU_INTR_S_SET_OFFSET 0x308 47 48 /* 49 * Define a list of Group 1 Secure interrupt properties as per GICv3 50 * terminology. On a GICv2 system or mode, the interrupts will be treated as 51 * Group 0 interrupts. 52 */ 53 #define CSS_G1S_IRQ_PROPS(grp) \ 54 INTR_PROP_DESC(CSS_IRQ_MHU, GIC_HIGHEST_SEC_PRIORITY, grp, \ 55 GIC_INTR_CFG_LEVEL), \ 56 INTR_PROP_DESC(CSS_IRQ_GPU_SMMU_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ 57 GIC_INTR_CFG_LEVEL), \ 58 INTR_PROP_DESC(CSS_IRQ_TZC, GIC_HIGHEST_SEC_PRIORITY, grp, \ 59 GIC_INTR_CFG_LEVEL), \ 60 INTR_PROP_DESC(CSS_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, grp, \ 61 GIC_INTR_CFG_LEVEL), \ 62 INTR_PROP_DESC(CSS_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 63 GIC_INTR_CFG_LEVEL) 64 65 #if CSS_USE_SCMI_SDS_DRIVER 66 /* Memory region for shared data storage */ 67 #define PLAT_ARM_SDS_MEM_BASE ARM_SHARED_RAM_BASE 68 #define PLAT_ARM_SDS_MEM_SIZE_MAX 0xDC0 /* 3520 bytes */ 69 /* 70 * The SCMI Channel is placed right after the SDS region 71 */ 72 #define CSS_SCMI_PAYLOAD_BASE (PLAT_ARM_SDS_MEM_BASE + PLAT_ARM_SDS_MEM_SIZE_MAX) 73 #define CSS_SCMI_MHU_DB_REG_OFF MHU_CPU_INTR_S_SET_OFFSET 74 75 /* Trusted mailbox base address common to all CSS */ 76 /* If SDS is present, then mailbox is at top of SRAM */ 77 #define PLAT_ARM_TRUSTED_MAILBOX_BASE (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE - 0x8) 78 79 /* Number of retries for SCP_RAM_READY flag */ 80 #define CSS_SCP_READY_10US_RETRIES 1000000 /* Effective timeout of 10000 ms */ 81 82 #else 83 /* 84 * SCP <=> AP boot configuration 85 * 86 * The SCP/AP boot configuration is a 32-bit word located at a known offset from 87 * the start of the Trusted SRAM. 88 * 89 * Note that the value stored at this address is only valid at boot time, before 90 * the SCP_BL2 image is transferred to SCP. 91 */ 92 #define SCP_BOOT_CFG_ADDR PLAT_CSS_SCP_COM_SHARED_MEM_BASE 93 94 /* Trusted mailbox base address common to all CSS */ 95 /* If SDS is not present, then the mailbox is at the bottom of SRAM */ 96 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 97 98 #endif /* CSS_USE_SCMI_SDS_DRIVER */ 99 100 #define CSS_MAP_DEVICE MAP_REGION_FLAT( \ 101 CSS_DEVICE_BASE, \ 102 CSS_DEVICE_SIZE, \ 103 MT_DEVICE | MT_RW | MT_SECURE) 104 105 #define CSS_MAP_NSRAM MAP_REGION_FLAT( \ 106 NSRAM_BASE, \ 107 NSRAM_SIZE, \ 108 MT_DEVICE | MT_RW | MT_NS) 109 110 #if defined(IMAGE_BL2U) 111 #define CSS_MAP_SCP_BL2U MAP_REGION_FLAT( \ 112 SCP_BL2U_BASE, \ 113 SCP_BL2U_LIMIT \ 114 - SCP_BL2U_BASE,\ 115 MT_RW_DATA | MT_SECURE) 116 #endif 117 118 /* Platform ID address */ 119 #define SSC_VERSION_OFFSET 0x040 120 121 #define SSC_VERSION_CONFIG_SHIFT 28 122 #define SSC_VERSION_MAJOR_REV_SHIFT 24 123 #define SSC_VERSION_MINOR_REV_SHIFT 20 124 #define SSC_VERSION_DESIGNER_ID_SHIFT 12 125 #define SSC_VERSION_PART_NUM_SHIFT 0x0 126 #define SSC_VERSION_CONFIG_MASK 0xf 127 #define SSC_VERSION_MAJOR_REV_MASK 0xf 128 #define SSC_VERSION_MINOR_REV_MASK 0xf 129 #define SSC_VERSION_DESIGNER_ID_MASK 0xff 130 #define SSC_VERSION_PART_NUM_MASK 0xfff 131 132 #define SID_SYSTEM_ID_PART_NUM_MASK 0xfff 133 134 /* SSC debug configuration registers */ 135 #define SSC_DBGCFG_SET 0x14 136 #define SSC_DBGCFG_CLR 0x18 137 138 #define SPIDEN_INT_CLR_SHIFT 6 139 #define SPIDEN_SEL_SET_SHIFT 7 140 141 #ifndef __ASSEMBLY__ 142 143 /* SSC_VERSION related accessors */ 144 145 /* Returns the part number of the platform */ 146 #define GET_SSC_VERSION_PART_NUM(val) \ 147 (((val) >> SSC_VERSION_PART_NUM_SHIFT) & \ 148 SSC_VERSION_PART_NUM_MASK) 149 150 /* Returns the configuration number of the platform */ 151 #define GET_SSC_VERSION_CONFIG(val) \ 152 (((val) >> SSC_VERSION_CONFIG_SHIFT) & \ 153 SSC_VERSION_CONFIG_MASK) 154 155 #endif /* __ASSEMBLY__ */ 156 157 /************************************************************************* 158 * Required platform porting definitions common to all 159 * ARM Compute SubSystems (CSS) 160 ************************************************************************/ 161 162 /* 163 * The loading of SCP images(SCP_BL2 or SCP_BL2U) is done if there 164 * respective base addresses are defined (i.e SCP_BL2_BASE, SCP_BL2U_BASE). 165 * Hence, `CSS_LOAD_SCP_IMAGES` needs to be set to 1 if BL2 needs to load 166 * an SCP_BL2/SCP_BL2U image. 167 */ 168 #if CSS_LOAD_SCP_IMAGES 169 170 #if ARM_BL31_IN_DRAM 171 #error "SCP_BL2 is not expected to be loaded by BL2 for ARM_BL31_IN_DRAM config" 172 #endif 173 174 /* 175 * Load address of SCP_BL2 in CSS platform ports 176 * SCP_BL2 is loaded to the same place as BL31 but it shouldn't overwrite BL1 177 * rw data or BL2. Once SCP_BL2 is transferred to the SCP, it is discarded and 178 * BL31 is loaded over the top. 179 */ 180 #define SCP_BL2_BASE (BL2_BASE - PLAT_CSS_MAX_SCP_BL2_SIZE) 181 #define SCP_BL2_LIMIT BL2_BASE 182 183 #define SCP_BL2U_BASE (BL2_BASE - PLAT_CSS_MAX_SCP_BL2U_SIZE) 184 #define SCP_BL2U_LIMIT BL2_BASE 185 #endif /* CSS_LOAD_SCP_IMAGES */ 186 187 /* Load address of Non-Secure Image for CSS platform ports */ 188 #define PLAT_ARM_NS_IMAGE_OFFSET U(0xE0000000) 189 190 /* TZC related constants */ 191 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT_ALL 192 193 /* 194 * Parsing of CPU and Cluster states, as returned by 'Get CSS Power State' SCP 195 * command 196 */ 197 #define CSS_CLUSTER_PWR_STATE_ON 0 198 #define CSS_CLUSTER_PWR_STATE_OFF 3 199 200 #define CSS_CPU_PWR_STATE_ON 1 201 #define CSS_CPU_PWR_STATE_OFF 0 202 #define CSS_CPU_PWR_STATE(state, n) (((state) >> (n)) & 1) 203 204 #endif /* CSS_DEF_H */ 205