1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch_helpers.h> 10 #include <bl31/bl31.h> 11 #include <bl31/interrupt_mgmt.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <common/interrupt_props.h> 15 #include <context.h> 16 #include <cortex_a57.h> 17 #include <denver.h> 18 #include <drivers/arm/gic_common.h> 19 #include <drivers/arm/gicv2.h> 20 #include <drivers/console.h> 21 #include <lib/el3_runtime/context_mgmt.h> 22 #include <lib/xlat_tables/xlat_tables_v2.h> 23 #include <plat/common/platform.h> 24 25 #include <mce.h> 26 #include <tegra_def.h> 27 #include <tegra_platform.h> 28 #include <tegra_private.h> 29 30 DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, CORTEX_A57_L2CTLR_EL1) 31 extern uint64_t tegra_enable_l2_ecc_parity_prot; 32 33 /******************************************************************************* 34 * Tegra186 CPU numbers in cluster #0 35 ******************************************************************************* 36 */ 37 #define TEGRA186_CLUSTER0_CORE2 2 38 #define TEGRA186_CLUSTER0_CORE3 3 39 40 /******************************************************************************* 41 * The Tegra power domain tree has a single system level power domain i.e. a 42 * single root node. The first entry in the power domain descriptor specifies 43 * the number of power domains at the highest power level. 44 ******************************************************************************* 45 */ 46 const unsigned char tegra_power_domain_tree_desc[] = { 47 /* No of root nodes */ 48 1, 49 /* No of clusters */ 50 PLATFORM_CLUSTER_COUNT, 51 /* No of CPU cores - cluster0 */ 52 PLATFORM_MAX_CPUS_PER_CLUSTER, 53 /* No of CPU cores - cluster1 */ 54 PLATFORM_MAX_CPUS_PER_CLUSTER 55 }; 56 57 /* 58 * Table of regions to map using the MMU. 59 */ 60 static const mmap_region_t tegra_mmap[] = { 61 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */ 62 MT_DEVICE | MT_RW | MT_SECURE), 63 MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */ 64 MT_DEVICE | MT_RW | MT_SECURE), 65 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */ 66 MT_DEVICE | MT_RW | MT_SECURE), 67 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */ 68 MT_DEVICE | MT_RW | MT_SECURE), 69 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB - UART A, B*/ 70 MT_DEVICE | MT_RW | MT_SECURE), 71 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000, /* 128KB - UART C, G */ 72 MT_DEVICE | MT_RW | MT_SECURE), 73 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000, /* 192KB - UART D, E, F */ 74 MT_DEVICE | MT_RW | MT_SECURE), 75 MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000, /* 64KB */ 76 MT_DEVICE | MT_RW | MT_SECURE), 77 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */ 78 MT_DEVICE | MT_RW | MT_SECURE), 79 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */ 80 MT_DEVICE | MT_RW | MT_SECURE), 81 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000, /* 64KB */ 82 MT_DEVICE | MT_RW | MT_SECURE), 83 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000, /* 64KB */ 84 MT_DEVICE | MT_RW | MT_SECURE), 85 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */ 86 MT_DEVICE | MT_RW | MT_SECURE), 87 MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */ 88 MT_DEVICE | MT_RW | MT_SECURE), 89 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000, /* 64KB */ 90 MT_DEVICE | MT_RW | MT_SECURE), 91 MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */ 92 MT_DEVICE | MT_RW | MT_SECURE), 93 MAP_REGION_FLAT(TEGRA_ARM_ACTMON_CTR_BASE, 0x20000, /* 128KB - ARM/Denver */ 94 MT_DEVICE | MT_RW | MT_SECURE), 95 MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000, /* 64KB */ 96 MT_DEVICE | MT_RW | MT_SECURE), 97 {0} 98 }; 99 100 /******************************************************************************* 101 * Set up the pagetables as per the platform memory map & initialize the MMU 102 ******************************************************************************/ 103 const mmap_region_t *plat_get_mmio_map(void) 104 { 105 /* MMIO space */ 106 return tegra_mmap; 107 } 108 109 /******************************************************************************* 110 * Handler to get the System Counter Frequency 111 ******************************************************************************/ 112 unsigned int plat_get_syscnt_freq2(void) 113 { 114 return 31250000; 115 } 116 117 /******************************************************************************* 118 * Maximum supported UART controllers 119 ******************************************************************************/ 120 #define TEGRA186_MAX_UART_PORTS 7 121 122 /******************************************************************************* 123 * This variable holds the UART port base addresses 124 ******************************************************************************/ 125 static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = { 126 0, /* undefined - treated as an error case */ 127 TEGRA_UARTA_BASE, 128 TEGRA_UARTB_BASE, 129 TEGRA_UARTC_BASE, 130 TEGRA_UARTD_BASE, 131 TEGRA_UARTE_BASE, 132 TEGRA_UARTF_BASE, 133 TEGRA_UARTG_BASE, 134 }; 135 136 /******************************************************************************* 137 * Retrieve the UART controller base to be used as the console 138 ******************************************************************************/ 139 uint32_t plat_get_console_from_id(int id) 140 { 141 if (id > TEGRA186_MAX_UART_PORTS) 142 return 0; 143 144 return tegra186_uart_addresses[id]; 145 } 146 147 /* represent chip-version as concatenation of major (15:12), minor (11:8) and subrev (7:0) */ 148 #define TEGRA186_VER_A02P 0x1201 149 150 /******************************************************************************* 151 * Handler for early platform setup 152 ******************************************************************************/ 153 void plat_early_platform_setup(void) 154 { 155 int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 156 uint32_t chip_subrev, val; 157 158 /* sanity check MCE firmware compatibility */ 159 mce_verify_firmware_version(); 160 161 /* 162 * Enable ECC and Parity Protection for Cortex-A57 CPUs 163 * for Tegra A02p SKUs 164 */ 165 if (impl != DENVER_IMPL) { 166 167 /* get the major, minor and sub-version values */ 168 chip_subrev = mmio_read_32(TEGRA_FUSE_BASE + OPT_SUBREVISION) & 169 SUBREVISION_MASK; 170 171 /* prepare chip version number */ 172 val = (tegra_get_chipid_major() << 12) | 173 (tegra_get_chipid_minor() << 8) | 174 chip_subrev; 175 176 /* enable L2 ECC for Tegra186 A02P and beyond */ 177 if (val >= TEGRA186_VER_A02P) { 178 179 val = read_l2ctlr_el1(); 180 val |= CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT; 181 write_l2ctlr_el1(val); 182 183 /* 184 * Set the flag to enable ECC/Parity Protection 185 * when we exit System Suspend or Cluster Powerdn 186 */ 187 tegra_enable_l2_ecc_parity_prot = 1; 188 } 189 } 190 } 191 192 /* Secure IRQs for Tegra186 */ 193 static const interrupt_prop_t tegra186_interrupt_props[] = { 194 INTR_PROP_DESC(TEGRA186_TOP_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY, 195 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE), 196 INTR_PROP_DESC(TEGRA186_AON_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY, 197 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE) 198 }; 199 200 /******************************************************************************* 201 * Initialize the GIC and SGIs 202 ******************************************************************************/ 203 void plat_gic_setup(void) 204 { 205 tegra_gic_setup(tegra186_interrupt_props, ARRAY_SIZE(tegra186_interrupt_props)); 206 207 /* 208 * Initialize the FIQ handler only if the platform supports any 209 * FIQ interrupt sources. 210 */ 211 if (sizeof(tegra186_interrupt_props) > 0) 212 tegra_fiq_handler_setup(); 213 } 214 215 /******************************************************************************* 216 * Return pointer to the BL31 params from previous bootloader 217 ******************************************************************************/ 218 struct tegra_bl31_params *plat_get_bl31_params(void) 219 { 220 uint32_t val; 221 222 val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO); 223 224 return (struct tegra_bl31_params *)(uintptr_t)val; 225 } 226 227 /******************************************************************************* 228 * Return pointer to the BL31 platform params from previous bootloader 229 ******************************************************************************/ 230 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 231 { 232 uint32_t val; 233 234 val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_HI); 235 236 return (plat_params_from_bl2_t *)(uintptr_t)val; 237 } 238 239 /******************************************************************************* 240 * This function implements a part of the critical interface between the psci 241 * generic layer and the platform that allows the former to query the platform 242 * to convert an MPIDR to a unique linear index. An error code (-1) is returned 243 * in case the MPIDR is invalid. 244 ******************************************************************************/ 245 int plat_core_pos_by_mpidr(u_register_t mpidr) 246 { 247 unsigned int cluster_id, cpu_id, pos; 248 249 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; 250 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; 251 252 /* 253 * Validate cluster_id by checking whether it represents 254 * one of the two clusters present on the platform. 255 */ 256 if (cluster_id >= PLATFORM_CLUSTER_COUNT) 257 return PSCI_E_NOT_PRESENT; 258 259 /* 260 * Validate cpu_id by checking whether it represents a CPU in 261 * one of the two clusters present on the platform. 262 */ 263 if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) 264 return PSCI_E_NOT_PRESENT; 265 266 /* calculate the core position */ 267 pos = cpu_id + (cluster_id << 2); 268 269 /* check for non-existent CPUs */ 270 if (pos == TEGRA186_CLUSTER0_CORE2 || pos == TEGRA186_CLUSTER0_CORE3) 271 return PSCI_E_NOT_PRESENT; 272 273 return pos; 274 } 275