1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <debug.h> 9 #include <mmio.h> 10 #include <m0_ctl.h> 11 #include <plat_private.h> 12 #include "dfs.h" 13 #include "dram.h" 14 #include "dram_spec_timing.h" 15 #include "string.h" 16 #include "soc.h" 17 #include "pmu.h" 18 19 #include <delay_timer.h> 20 21 #define ENPER_CS_TRAINING_FREQ (666) 22 #define TDFI_LAT_THRESHOLD_FREQ (928) 23 #define PHY_DLL_BYPASS_FREQ (260) 24 25 static const struct pll_div dpll_rates_table[] = { 26 27 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2 */ 28 {.mhz = 928, .refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1}, 29 {.mhz = 800, .refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}, 30 {.mhz = 732, .refdiv = 1, .fbdiv = 61, .postdiv1 = 2, .postdiv2 = 1}, 31 {.mhz = 666, .refdiv = 1, .fbdiv = 111, .postdiv1 = 4, .postdiv2 = 1}, 32 {.mhz = 600, .refdiv = 1, .fbdiv = 50, .postdiv1 = 2, .postdiv2 = 1}, 33 {.mhz = 528, .refdiv = 1, .fbdiv = 66, .postdiv1 = 3, .postdiv2 = 1}, 34 {.mhz = 400, .refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1}, 35 {.mhz = 300, .refdiv = 1, .fbdiv = 50, .postdiv1 = 4, .postdiv2 = 1}, 36 {.mhz = 200, .refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 2}, 37 }; 38 39 struct rk3399_dram_status { 40 uint32_t current_index; 41 uint32_t index_freq[2]; 42 uint32_t boot_freq; 43 uint32_t low_power_stat; 44 struct timing_related_config timing_config; 45 struct drv_odt_lp_config drv_odt_lp_cfg; 46 }; 47 48 struct rk3399_saved_status { 49 uint32_t freq; 50 uint32_t low_power_stat; 51 uint32_t odt; 52 }; 53 54 static struct rk3399_dram_status rk3399_dram_status; 55 static struct rk3399_saved_status rk3399_suspend_status; 56 static uint32_t wrdqs_delay_val[2][2][4]; 57 58 static struct rk3399_sdram_default_config ddr3_default_config = { 59 .bl = 8, 60 .ap = 0, 61 .burst_ref_cnt = 1, 62 .zqcsi = 0 63 }; 64 65 static struct rk3399_sdram_default_config lpddr3_default_config = { 66 .bl = 8, 67 .ap = 0, 68 .burst_ref_cnt = 1, 69 .zqcsi = 0 70 }; 71 72 static struct rk3399_sdram_default_config lpddr4_default_config = { 73 .bl = 16, 74 .ap = 0, 75 .caodt = 240, 76 .burst_ref_cnt = 1, 77 .zqcsi = 0 78 }; 79 80 static uint32_t get_cs_die_capability(struct rk3399_sdram_params *sdram_config, 81 uint8_t channel, uint8_t cs) 82 { 83 struct rk3399_sdram_channel *ch = &sdram_config->ch[channel]; 84 uint32_t bandwidth; 85 uint32_t die_bandwidth; 86 uint32_t die; 87 uint32_t cs_cap; 88 uint32_t row; 89 90 row = cs == 0 ? ch->cs0_row : ch->cs1_row; 91 bandwidth = 8 * (1 << ch->bw); 92 die_bandwidth = 8 * (1 << ch->dbw); 93 die = bandwidth / die_bandwidth; 94 cs_cap = (1 << (row + ((1 << ch->bk) / 4 + 1) + ch->col + 95 (bandwidth / 16))); 96 if (ch->row_3_4) 97 cs_cap = cs_cap * 3 / 4; 98 99 return (cs_cap / die); 100 } 101 102 static void get_dram_drv_odt_val(uint32_t dram_type, 103 struct drv_odt_lp_config *drv_config) 104 { 105 uint32_t tmp; 106 uint32_t mr1_val, mr3_val, mr11_val; 107 108 switch (dram_type) { 109 case DDR3: 110 mr1_val = (mmio_read_32(CTL_REG(0, 133)) >> 16) & 0xffff; 111 tmp = ((mr1_val >> 1) & 1) | ((mr1_val >> 4) & 1); 112 if (tmp) 113 drv_config->dram_side_drv = 34; 114 else 115 drv_config->dram_side_drv = 40; 116 tmp = ((mr1_val >> 2) & 1) | ((mr1_val >> 5) & 1) | 117 ((mr1_val >> 7) & 1); 118 if (tmp == 0) 119 drv_config->dram_side_dq_odt = 0; 120 else if (tmp == 1) 121 drv_config->dram_side_dq_odt = 60; 122 else if (tmp == 3) 123 drv_config->dram_side_dq_odt = 40; 124 else 125 drv_config->dram_side_dq_odt = 120; 126 break; 127 case LPDDR3: 128 mr3_val = mmio_read_32(CTL_REG(0, 138)) & 0xf; 129 mr11_val = (mmio_read_32(CTL_REG(0, 139)) >> 24) & 0x3; 130 if (mr3_val == 0xb) 131 drv_config->dram_side_drv = 3448; 132 else if (mr3_val == 0xa) 133 drv_config->dram_side_drv = 4048; 134 else if (mr3_val == 0x9) 135 drv_config->dram_side_drv = 3440; 136 else if (mr3_val == 0x4) 137 drv_config->dram_side_drv = 60; 138 else if (mr3_val == 0x3) 139 drv_config->dram_side_drv = 48; 140 else if (mr3_val == 0x2) 141 drv_config->dram_side_drv = 40; 142 else 143 drv_config->dram_side_drv = 34; 144 145 if (mr11_val == 1) 146 drv_config->dram_side_dq_odt = 60; 147 else if (mr11_val == 2) 148 drv_config->dram_side_dq_odt = 120; 149 else if (mr11_val == 0) 150 drv_config->dram_side_dq_odt = 0; 151 else 152 drv_config->dram_side_dq_odt = 240; 153 break; 154 case LPDDR4: 155 default: 156 mr3_val = (mmio_read_32(CTL_REG(0, 138)) >> 3) & 0x7; 157 mr11_val = (mmio_read_32(CTL_REG(0, 139)) >> 24) & 0xff; 158 159 if ((mr3_val == 0) || (mr3_val == 7)) 160 drv_config->dram_side_drv = 40; 161 else 162 drv_config->dram_side_drv = 240 / mr3_val; 163 164 tmp = mr11_val & 0x7; 165 if ((tmp == 7) || (tmp == 0)) 166 drv_config->dram_side_dq_odt = 0; 167 else 168 drv_config->dram_side_dq_odt = 240 / tmp; 169 170 tmp = (mr11_val >> 4) & 0x7; 171 if ((tmp == 7) || (tmp == 0)) 172 drv_config->dram_side_ca_odt = 0; 173 else 174 drv_config->dram_side_ca_odt = 240 / tmp; 175 break; 176 } 177 } 178 179 static void sdram_timing_cfg_init(struct timing_related_config *ptiming_config, 180 struct rk3399_sdram_params *sdram_params, 181 struct drv_odt_lp_config *drv_config) 182 { 183 uint32_t i, j; 184 185 for (i = 0; i < sdram_params->num_channels; i++) { 186 ptiming_config->dram_info[i].speed_rate = DDR3_DEFAULT; 187 ptiming_config->dram_info[i].cs_cnt = sdram_params->ch[i].rank; 188 for (j = 0; j < sdram_params->ch[i].rank; j++) { 189 ptiming_config->dram_info[i].per_die_capability[j] = 190 get_cs_die_capability(sdram_params, i, j); 191 } 192 } 193 ptiming_config->dram_type = sdram_params->dramtype; 194 ptiming_config->ch_cnt = sdram_params->num_channels; 195 switch (sdram_params->dramtype) { 196 case DDR3: 197 ptiming_config->bl = ddr3_default_config.bl; 198 ptiming_config->ap = ddr3_default_config.ap; 199 break; 200 case LPDDR3: 201 ptiming_config->bl = lpddr3_default_config.bl; 202 ptiming_config->ap = lpddr3_default_config.ap; 203 break; 204 case LPDDR4: 205 ptiming_config->bl = lpddr4_default_config.bl; 206 ptiming_config->ap = lpddr4_default_config.ap; 207 ptiming_config->rdbi = 0; 208 ptiming_config->wdbi = 0; 209 break; 210 } 211 ptiming_config->dramds = drv_config->dram_side_drv; 212 ptiming_config->dramodt = drv_config->dram_side_dq_odt; 213 ptiming_config->caodt = drv_config->dram_side_ca_odt; 214 ptiming_config->odt = (mmio_read_32(PHY_REG(0, 5)) >> 16) & 0x1; 215 } 216 217 struct lat_adj_pair { 218 uint32_t cl; 219 uint32_t rdlat_adj; 220 uint32_t cwl; 221 uint32_t wrlat_adj; 222 }; 223 224 const struct lat_adj_pair ddr3_lat_adj[] = { 225 {6, 5, 5, 4}, 226 {8, 7, 6, 5}, 227 {10, 9, 7, 6}, 228 {11, 9, 8, 7}, 229 {13, 0xb, 9, 8}, 230 {14, 0xb, 0xa, 9} 231 }; 232 233 const struct lat_adj_pair lpddr3_lat_adj[] = { 234 {3, 2, 1, 0}, 235 {6, 5, 3, 2}, 236 {8, 7, 4, 3}, 237 {9, 8, 5, 4}, 238 {10, 9, 6, 5}, 239 {11, 9, 6, 5}, 240 {12, 0xa, 6, 5}, 241 {14, 0xc, 8, 7}, 242 {16, 0xd, 8, 7} 243 }; 244 245 const struct lat_adj_pair lpddr4_lat_adj[] = { 246 {6, 5, 4, 2}, 247 {10, 9, 6, 4}, 248 {14, 0xc, 8, 6}, 249 {20, 0x11, 0xa, 8}, 250 {24, 0x15, 0xc, 0xa}, 251 {28, 0x18, 0xe, 0xc}, 252 {32, 0x1b, 0x10, 0xe}, 253 {36, 0x1e, 0x12, 0x10} 254 }; 255 256 static uint32_t get_rdlat_adj(uint32_t dram_type, uint32_t cl) 257 { 258 const struct lat_adj_pair *p; 259 uint32_t cnt; 260 uint32_t i; 261 262 if (dram_type == DDR3) { 263 p = ddr3_lat_adj; 264 cnt = ARRAY_SIZE(ddr3_lat_adj); 265 } else if (dram_type == LPDDR3) { 266 p = lpddr3_lat_adj; 267 cnt = ARRAY_SIZE(lpddr3_lat_adj); 268 } else { 269 p = lpddr4_lat_adj; 270 cnt = ARRAY_SIZE(lpddr4_lat_adj); 271 } 272 273 for (i = 0; i < cnt; i++) { 274 if (cl == p[i].cl) 275 return p[i].rdlat_adj; 276 } 277 /* fail */ 278 return 0xff; 279 } 280 281 static uint32_t get_wrlat_adj(uint32_t dram_type, uint32_t cwl) 282 { 283 const struct lat_adj_pair *p; 284 uint32_t cnt; 285 uint32_t i; 286 287 if (dram_type == DDR3) { 288 p = ddr3_lat_adj; 289 cnt = ARRAY_SIZE(ddr3_lat_adj); 290 } else if (dram_type == LPDDR3) { 291 p = lpddr3_lat_adj; 292 cnt = ARRAY_SIZE(lpddr3_lat_adj); 293 } else { 294 p = lpddr4_lat_adj; 295 cnt = ARRAY_SIZE(lpddr4_lat_adj); 296 } 297 298 for (i = 0; i < cnt; i++) { 299 if (cwl == p[i].cwl) 300 return p[i].wrlat_adj; 301 } 302 /* fail */ 303 return 0xff; 304 } 305 306 #define PI_REGS_DIMM_SUPPORT (0) 307 #define PI_ADD_LATENCY (0) 308 #define PI_DOUBLEFREEK (1) 309 310 #define PI_PAD_DELAY_PS_VALUE (1000) 311 #define PI_IE_ENABLE_VALUE (3000) 312 #define PI_TSEL_ENABLE_VALUE (700) 313 314 static uint32_t get_pi_rdlat_adj(struct dram_timing_t *pdram_timing) 315 { 316 /*[DLLSUBTYPE2] == "STD_DENALI_HS" */ 317 uint32_t rdlat, delay_adder, ie_enable, hs_offset, tsel_adder, 318 extra_adder, tsel_enable; 319 320 ie_enable = PI_IE_ENABLE_VALUE; 321 tsel_enable = PI_TSEL_ENABLE_VALUE; 322 323 rdlat = pdram_timing->cl + PI_ADD_LATENCY; 324 delay_adder = ie_enable / (1000000 / pdram_timing->mhz); 325 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 326 delay_adder++; 327 hs_offset = 0; 328 tsel_adder = 0; 329 extra_adder = 0; 330 /* rdlat = rdlat - (PREAMBLE_SUPPORT & 0x1); */ 331 tsel_adder = tsel_enable / (1000000 / pdram_timing->mhz); 332 if ((tsel_enable % (1000000 / pdram_timing->mhz)) != 0) 333 tsel_adder++; 334 delay_adder = delay_adder - 1; 335 if (tsel_adder > delay_adder) 336 extra_adder = tsel_adder - delay_adder; 337 else 338 extra_adder = 0; 339 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) 340 hs_offset = 2; 341 else 342 hs_offset = 1; 343 344 if (delay_adder > (rdlat - 1 - hs_offset)) { 345 rdlat = rdlat - tsel_adder; 346 } else { 347 if ((rdlat - delay_adder) < 2) 348 rdlat = 2; 349 else 350 rdlat = rdlat - delay_adder - extra_adder; 351 } 352 353 return rdlat; 354 } 355 356 static uint32_t get_pi_wrlat(struct dram_timing_t *pdram_timing, 357 struct timing_related_config *timing_config) 358 { 359 uint32_t tmp; 360 361 if (timing_config->dram_type == LPDDR3) { 362 tmp = pdram_timing->cl; 363 if (tmp >= 14) 364 tmp = 8; 365 else if (tmp >= 10) 366 tmp = 6; 367 else if (tmp == 9) 368 tmp = 5; 369 else if (tmp == 8) 370 tmp = 4; 371 else if (tmp == 6) 372 tmp = 3; 373 else 374 tmp = 1; 375 } else { 376 tmp = 1; 377 } 378 379 return tmp; 380 } 381 382 static uint32_t get_pi_wrlat_adj(struct dram_timing_t *pdram_timing, 383 struct timing_related_config *timing_config) 384 { 385 return get_pi_wrlat(pdram_timing, timing_config) + PI_ADD_LATENCY - 1; 386 } 387 388 static uint32_t get_pi_tdfi_phy_rdlat(struct dram_timing_t *pdram_timing, 389 struct timing_related_config *timing_config) 390 { 391 /* [DLLSUBTYPE2] == "STD_DENALI_HS" */ 392 uint32_t cas_lat, delay_adder, ie_enable, hs_offset, ie_delay_adder; 393 uint32_t mem_delay_ps, round_trip_ps; 394 uint32_t phy_internal_delay, lpddr_adder, dfi_adder, rdlat_delay; 395 396 ie_enable = PI_IE_ENABLE_VALUE; 397 398 delay_adder = ie_enable / (1000000 / pdram_timing->mhz); 399 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 400 delay_adder++; 401 delay_adder = delay_adder - 1; 402 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) 403 hs_offset = 2; 404 else 405 hs_offset = 1; 406 407 cas_lat = pdram_timing->cl + PI_ADD_LATENCY; 408 409 if (delay_adder > (cas_lat - 1 - hs_offset)) { 410 ie_delay_adder = 0; 411 } else { 412 ie_delay_adder = ie_enable / (1000000 / pdram_timing->mhz); 413 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 414 ie_delay_adder++; 415 } 416 417 if (timing_config->dram_type == DDR3) { 418 mem_delay_ps = 0; 419 } else if (timing_config->dram_type == LPDDR4) { 420 mem_delay_ps = 3600; 421 } else if (timing_config->dram_type == LPDDR3) { 422 mem_delay_ps = 5500; 423 } else { 424 NOTICE("get_pi_tdfi_phy_rdlat:dramtype unsupport\n"); 425 return 0; 426 } 427 round_trip_ps = 1100 + 500 + mem_delay_ps + 500 + 600; 428 delay_adder = round_trip_ps / (1000000 / pdram_timing->mhz); 429 if ((round_trip_ps % (1000000 / pdram_timing->mhz)) != 0) 430 delay_adder++; 431 432 phy_internal_delay = 5 + 2 + 4; 433 lpddr_adder = mem_delay_ps / (1000000 / pdram_timing->mhz); 434 if ((mem_delay_ps % (1000000 / pdram_timing->mhz)) != 0) 435 lpddr_adder++; 436 dfi_adder = 0; 437 phy_internal_delay = phy_internal_delay + 2; 438 rdlat_delay = delay_adder + phy_internal_delay + 439 ie_delay_adder + lpddr_adder + dfi_adder; 440 441 rdlat_delay = rdlat_delay + 2; 442 return rdlat_delay; 443 } 444 445 static uint32_t get_pi_todtoff_min(struct dram_timing_t *pdram_timing, 446 struct timing_related_config *timing_config) 447 { 448 uint32_t tmp, todtoff_min_ps; 449 450 if (timing_config->dram_type == LPDDR3) 451 todtoff_min_ps = 2500; 452 else if (timing_config->dram_type == LPDDR4) 453 todtoff_min_ps = 1500; 454 else 455 todtoff_min_ps = 0; 456 /* todtoff_min */ 457 tmp = todtoff_min_ps / (1000000 / pdram_timing->mhz); 458 if ((todtoff_min_ps % (1000000 / pdram_timing->mhz)) != 0) 459 tmp++; 460 return tmp; 461 } 462 463 static uint32_t get_pi_todtoff_max(struct dram_timing_t *pdram_timing, 464 struct timing_related_config *timing_config) 465 { 466 uint32_t tmp, todtoff_max_ps; 467 468 if ((timing_config->dram_type == LPDDR4) 469 || (timing_config->dram_type == LPDDR3)) 470 todtoff_max_ps = 3500; 471 else 472 todtoff_max_ps = 0; 473 474 /* todtoff_max */ 475 tmp = todtoff_max_ps / (1000000 / pdram_timing->mhz); 476 if ((todtoff_max_ps % (1000000 / pdram_timing->mhz)) != 0) 477 tmp++; 478 return tmp; 479 } 480 481 static void gen_rk3399_ctl_params_f0(struct timing_related_config 482 *timing_config, 483 struct dram_timing_t *pdram_timing) 484 { 485 uint32_t i; 486 uint32_t tmp, tmp1; 487 488 for (i = 0; i < timing_config->ch_cnt; i++) { 489 if (timing_config->dram_type == DDR3) { 490 tmp = ((700000 + 10) * timing_config->freq + 491 999) / 1000; 492 tmp += pdram_timing->txsnr + (pdram_timing->tmrd * 3) + 493 pdram_timing->tmod + pdram_timing->tzqinit; 494 mmio_write_32(CTL_REG(i, 5), tmp); 495 496 mmio_clrsetbits_32(CTL_REG(i, 22), 0xffff, 497 pdram_timing->tdllk); 498 499 mmio_write_32(CTL_REG(i, 32), 500 (pdram_timing->tmod << 8) | 501 pdram_timing->tmrd); 502 503 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16, 504 (pdram_timing->txsr - 505 pdram_timing->trcd) << 16); 506 } else if (timing_config->dram_type == LPDDR4) { 507 mmio_write_32(CTL_REG(i, 5), pdram_timing->tinit1 + 508 pdram_timing->tinit3); 509 mmio_write_32(CTL_REG(i, 32), 510 (pdram_timing->tmrd << 8) | 511 pdram_timing->tmrd); 512 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16, 513 pdram_timing->txsr << 16); 514 } else { 515 mmio_write_32(CTL_REG(i, 5), pdram_timing->tinit1); 516 mmio_write_32(CTL_REG(i, 7), pdram_timing->tinit4); 517 mmio_write_32(CTL_REG(i, 32), 518 (pdram_timing->tmrd << 8) | 519 pdram_timing->tmrd); 520 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16, 521 pdram_timing->txsr << 16); 522 } 523 mmio_write_32(CTL_REG(i, 6), pdram_timing->tinit3); 524 mmio_write_32(CTL_REG(i, 8), pdram_timing->tinit5); 525 mmio_clrsetbits_32(CTL_REG(i, 23), (0x7f << 16), 526 ((pdram_timing->cl * 2) << 16)); 527 mmio_clrsetbits_32(CTL_REG(i, 23), (0x1f << 24), 528 (pdram_timing->cwl << 24)); 529 mmio_clrsetbits_32(CTL_REG(i, 24), 0x3f, pdram_timing->al); 530 mmio_clrsetbits_32(CTL_REG(i, 26), 0xffff << 16, 531 (pdram_timing->trc << 24) | 532 (pdram_timing->trrd << 16)); 533 mmio_write_32(CTL_REG(i, 27), 534 (pdram_timing->tfaw << 24) | 535 (pdram_timing->trppb << 16) | 536 (pdram_timing->twtr << 8) | 537 pdram_timing->tras_min); 538 539 mmio_clrsetbits_32(CTL_REG(i, 31), 0xff << 24, 540 max(4, pdram_timing->trtp) << 24); 541 mmio_write_32(CTL_REG(i, 33), (pdram_timing->tcke << 24) | 542 pdram_timing->tras_max); 543 mmio_clrsetbits_32(CTL_REG(i, 34), 0xff, 544 max(1, pdram_timing->tckesr)); 545 mmio_clrsetbits_32(CTL_REG(i, 39), 546 (0x3f << 16) | (0xff << 8), 547 (pdram_timing->twr << 16) | 548 (pdram_timing->trcd << 8)); 549 mmio_clrsetbits_32(CTL_REG(i, 42), 0x1f << 16, 550 pdram_timing->tmrz << 16); 551 tmp = pdram_timing->tdal ? pdram_timing->tdal : 552 (pdram_timing->twr + pdram_timing->trp); 553 mmio_clrsetbits_32(CTL_REG(i, 44), 0xff, tmp); 554 mmio_clrsetbits_32(CTL_REG(i, 45), 0xff, pdram_timing->trp); 555 mmio_write_32(CTL_REG(i, 48), 556 ((pdram_timing->trefi - 8) << 16) | 557 pdram_timing->trfc); 558 mmio_clrsetbits_32(CTL_REG(i, 52), 0xffff, pdram_timing->txp); 559 mmio_clrsetbits_32(CTL_REG(i, 53), 0xffff << 16, 560 pdram_timing->txpdll << 16); 561 mmio_clrsetbits_32(CTL_REG(i, 55), 0xf << 24, 562 pdram_timing->tcscke << 24); 563 mmio_clrsetbits_32(CTL_REG(i, 55), 0xff, pdram_timing->tmrri); 564 mmio_write_32(CTL_REG(i, 56), 565 (pdram_timing->tzqcke << 24) | 566 (pdram_timing->tmrwckel << 16) | 567 (pdram_timing->tckehcs << 8) | 568 pdram_timing->tckelcs); 569 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff, pdram_timing->txsnr); 570 mmio_clrsetbits_32(CTL_REG(i, 62), 0xffff << 16, 571 (pdram_timing->tckehcmd << 24) | 572 (pdram_timing->tckelcmd << 16)); 573 mmio_write_32(CTL_REG(i, 63), 574 (pdram_timing->tckelpd << 24) | 575 (pdram_timing->tescke << 16) | 576 (pdram_timing->tsr << 8) | 577 pdram_timing->tckckel); 578 mmio_clrsetbits_32(CTL_REG(i, 64), 0xfff, 579 (pdram_timing->tcmdcke << 8) | 580 pdram_timing->tcsckeh); 581 mmio_clrsetbits_32(CTL_REG(i, 92), 0xffff << 8, 582 (pdram_timing->tcksrx << 16) | 583 (pdram_timing->tcksre << 8)); 584 mmio_clrsetbits_32(CTL_REG(i, 108), 0x1 << 24, 585 (timing_config->dllbp << 24)); 586 mmio_clrsetbits_32(CTL_REG(i, 122), 0x3ff << 16, 587 (pdram_timing->tvrcg_enable << 16)); 588 mmio_write_32(CTL_REG(i, 123), (pdram_timing->tfc_long << 16) | 589 pdram_timing->tvrcg_disable); 590 mmio_write_32(CTL_REG(i, 124), 591 (pdram_timing->tvref_long << 16) | 592 (pdram_timing->tckfspx << 8) | 593 pdram_timing->tckfspe); 594 mmio_write_32(CTL_REG(i, 133), (pdram_timing->mr[1] << 16) | 595 pdram_timing->mr[0]); 596 mmio_clrsetbits_32(CTL_REG(i, 134), 0xffff, 597 pdram_timing->mr[2]); 598 mmio_clrsetbits_32(CTL_REG(i, 138), 0xffff, 599 pdram_timing->mr[3]); 600 mmio_clrsetbits_32(CTL_REG(i, 139), 0xff << 24, 601 pdram_timing->mr11 << 24); 602 mmio_write_32(CTL_REG(i, 147), 603 (pdram_timing->mr[1] << 16) | 604 pdram_timing->mr[0]); 605 mmio_clrsetbits_32(CTL_REG(i, 148), 0xffff, 606 pdram_timing->mr[2]); 607 mmio_clrsetbits_32(CTL_REG(i, 152), 0xffff, 608 pdram_timing->mr[3]); 609 mmio_clrsetbits_32(CTL_REG(i, 153), 0xff << 24, 610 pdram_timing->mr11 << 24); 611 if (timing_config->dram_type == LPDDR4) { 612 mmio_clrsetbits_32(CTL_REG(i, 140), 0xffff << 16, 613 pdram_timing->mr12 << 16); 614 mmio_clrsetbits_32(CTL_REG(i, 142), 0xffff << 16, 615 pdram_timing->mr14 << 16); 616 mmio_clrsetbits_32(CTL_REG(i, 145), 0xffff << 16, 617 pdram_timing->mr22 << 16); 618 mmio_clrsetbits_32(CTL_REG(i, 154), 0xffff << 16, 619 pdram_timing->mr12 << 16); 620 mmio_clrsetbits_32(CTL_REG(i, 156), 0xffff << 16, 621 pdram_timing->mr14 << 16); 622 mmio_clrsetbits_32(CTL_REG(i, 159), 0xffff << 16, 623 pdram_timing->mr22 << 16); 624 } 625 mmio_clrsetbits_32(CTL_REG(i, 179), 0xfff << 8, 626 pdram_timing->tzqinit << 8); 627 mmio_write_32(CTL_REG(i, 180), (pdram_timing->tzqcs << 16) | 628 (pdram_timing->tzqinit / 2)); 629 mmio_write_32(CTL_REG(i, 181), (pdram_timing->tzqlat << 16) | 630 pdram_timing->tzqcal); 631 mmio_clrsetbits_32(CTL_REG(i, 212), 0xff << 8, 632 pdram_timing->todton << 8); 633 634 if (timing_config->odt) { 635 mmio_setbits_32(CTL_REG(i, 213), 1 << 16); 636 if (timing_config->freq < 400) 637 tmp = 4 << 24; 638 else 639 tmp = 8 << 24; 640 } else { 641 mmio_clrbits_32(CTL_REG(i, 213), 1 << 16); 642 tmp = 2 << 24; 643 } 644 645 mmio_clrsetbits_32(CTL_REG(i, 216), 0x1f << 24, tmp); 646 mmio_clrsetbits_32(CTL_REG(i, 221), (0x3 << 16) | (0xf << 8), 647 (pdram_timing->tdqsck << 16) | 648 (pdram_timing->tdqsck_max << 8)); 649 tmp = 650 (get_wrlat_adj(timing_config->dram_type, pdram_timing->cwl) 651 << 8) | get_rdlat_adj(timing_config->dram_type, 652 pdram_timing->cl); 653 mmio_clrsetbits_32(CTL_REG(i, 284), 0xffff, tmp); 654 mmio_clrsetbits_32(CTL_REG(i, 82), 0xffff << 16, 655 (4 * pdram_timing->trefi) << 16); 656 657 mmio_clrsetbits_32(CTL_REG(i, 83), 0xffff, 658 (2 * pdram_timing->trefi) & 0xffff); 659 660 if ((timing_config->dram_type == LPDDR3) || 661 (timing_config->dram_type == LPDDR4)) { 662 tmp = get_pi_wrlat(pdram_timing, timing_config); 663 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 664 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 665 } else { 666 tmp = 0; 667 } 668 mmio_clrsetbits_32(CTL_REG(i, 214), 0x3f << 16, 669 (tmp & 0x3f) << 16); 670 671 if ((timing_config->dram_type == LPDDR3) || 672 (timing_config->dram_type == LPDDR4)) { 673 /* min_rl_preamble = cl+TDQSCK_MIN -1 */ 674 tmp = pdram_timing->cl + 675 get_pi_todtoff_min(pdram_timing, timing_config) - 1; 676 /* todtoff_max */ 677 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 678 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 679 } else { 680 tmp = pdram_timing->cl - pdram_timing->cwl; 681 } 682 mmio_clrsetbits_32(CTL_REG(i, 215), 0x3f << 8, 683 (tmp & 0x3f) << 8); 684 685 mmio_clrsetbits_32(CTL_REG(i, 275), 0xff << 16, 686 (get_pi_tdfi_phy_rdlat(pdram_timing, 687 timing_config) & 688 0xff) << 16); 689 690 mmio_clrsetbits_32(CTL_REG(i, 277), 0xffff, 691 (2 * pdram_timing->trefi) & 0xffff); 692 693 mmio_clrsetbits_32(CTL_REG(i, 282), 0xffff, 694 (2 * pdram_timing->trefi) & 0xffff); 695 696 mmio_write_32(CTL_REG(i, 283), 20 * pdram_timing->trefi); 697 698 /* CTL_308 TDFI_CALVL_CAPTURE_F0:RW:16:10 */ 699 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 700 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 701 tmp1++; 702 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 703 mmio_clrsetbits_32(CTL_REG(i, 308), 0x3ff << 16, tmp << 16); 704 705 /* CTL_308 TDFI_CALVL_CC_F0:RW:0:10 */ 706 tmp = tmp + 18; 707 mmio_clrsetbits_32(CTL_REG(i, 308), 0x3ff, tmp); 708 709 /* CTL_314 TDFI_WRCSLAT_F0:RW:8:8 */ 710 tmp1 = get_pi_wrlat_adj(pdram_timing, timing_config); 711 if (timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) { 712 if (tmp1 == 0) 713 tmp = 0; 714 else if (tmp1 < 5) 715 tmp = tmp1 - 1; 716 else 717 tmp = tmp1 - 5; 718 } else { 719 tmp = tmp1 - 2; 720 } 721 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 8, tmp << 8); 722 723 /* CTL_314 TDFI_RDCSLAT_F0:RW:0:8 */ 724 if ((timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) && 725 (pdram_timing->cl >= 5)) 726 tmp = pdram_timing->cl - 5; 727 else 728 tmp = pdram_timing->cl - 2; 729 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff, tmp); 730 } 731 } 732 733 static void gen_rk3399_ctl_params_f1(struct timing_related_config 734 *timing_config, 735 struct dram_timing_t *pdram_timing) 736 { 737 uint32_t i; 738 uint32_t tmp, tmp1; 739 740 for (i = 0; i < timing_config->ch_cnt; i++) { 741 if (timing_config->dram_type == DDR3) { 742 tmp = 743 ((700000 + 10) * timing_config->freq + 999) / 1000; 744 tmp += pdram_timing->txsnr + (pdram_timing->tmrd * 3) + 745 pdram_timing->tmod + pdram_timing->tzqinit; 746 mmio_write_32(CTL_REG(i, 9), tmp); 747 mmio_clrsetbits_32(CTL_REG(i, 22), 0xffff << 16, 748 pdram_timing->tdllk << 16); 749 mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00, 750 (pdram_timing->tmod << 24) | 751 (pdram_timing->tmrd << 16) | 752 (pdram_timing->trtp << 8)); 753 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16, 754 (pdram_timing->txsr - 755 pdram_timing->trcd) << 16); 756 } else if (timing_config->dram_type == LPDDR4) { 757 mmio_write_32(CTL_REG(i, 9), pdram_timing->tinit1 + 758 pdram_timing->tinit3); 759 mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00, 760 (pdram_timing->tmrd << 24) | 761 (pdram_timing->tmrd << 16) | 762 (pdram_timing->trtp << 8)); 763 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16, 764 pdram_timing->txsr << 16); 765 } else { 766 mmio_write_32(CTL_REG(i, 9), pdram_timing->tinit1); 767 mmio_write_32(CTL_REG(i, 11), pdram_timing->tinit4); 768 mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00, 769 (pdram_timing->tmrd << 24) | 770 (pdram_timing->tmrd << 16) | 771 (pdram_timing->trtp << 8)); 772 mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16, 773 pdram_timing->txsr << 16); 774 } 775 mmio_write_32(CTL_REG(i, 10), pdram_timing->tinit3); 776 mmio_write_32(CTL_REG(i, 12), pdram_timing->tinit5); 777 mmio_clrsetbits_32(CTL_REG(i, 24), (0x7f << 8), 778 ((pdram_timing->cl * 2) << 8)); 779 mmio_clrsetbits_32(CTL_REG(i, 24), (0x1f << 16), 780 (pdram_timing->cwl << 16)); 781 mmio_clrsetbits_32(CTL_REG(i, 24), 0x3f << 24, 782 pdram_timing->al << 24); 783 mmio_clrsetbits_32(CTL_REG(i, 28), 0xffffff00, 784 (pdram_timing->tras_min << 24) | 785 (pdram_timing->trc << 16) | 786 (pdram_timing->trrd << 8)); 787 mmio_clrsetbits_32(CTL_REG(i, 29), 0xffffff, 788 (pdram_timing->tfaw << 16) | 789 (pdram_timing->trppb << 8) | 790 pdram_timing->twtr); 791 mmio_write_32(CTL_REG(i, 35), (pdram_timing->tcke << 24) | 792 pdram_timing->tras_max); 793 mmio_clrsetbits_32(CTL_REG(i, 36), 0xff, 794 max(1, pdram_timing->tckesr)); 795 mmio_clrsetbits_32(CTL_REG(i, 39), (0xff << 24), 796 (pdram_timing->trcd << 24)); 797 mmio_clrsetbits_32(CTL_REG(i, 40), 0x3f, pdram_timing->twr); 798 mmio_clrsetbits_32(CTL_REG(i, 42), 0x1f << 24, 799 pdram_timing->tmrz << 24); 800 tmp = pdram_timing->tdal ? pdram_timing->tdal : 801 (pdram_timing->twr + pdram_timing->trp); 802 mmio_clrsetbits_32(CTL_REG(i, 44), 0xff << 8, tmp << 8); 803 mmio_clrsetbits_32(CTL_REG(i, 45), 0xff << 8, 804 pdram_timing->trp << 8); 805 mmio_write_32(CTL_REG(i, 49), 806 ((pdram_timing->trefi - 8) << 16) | 807 pdram_timing->trfc); 808 mmio_clrsetbits_32(CTL_REG(i, 52), 0xffff << 16, 809 pdram_timing->txp << 16); 810 mmio_clrsetbits_32(CTL_REG(i, 54), 0xffff, 811 pdram_timing->txpdll); 812 mmio_clrsetbits_32(CTL_REG(i, 55), 0xff << 8, 813 pdram_timing->tmrri << 8); 814 mmio_write_32(CTL_REG(i, 57), (pdram_timing->tmrwckel << 24) | 815 (pdram_timing->tckehcs << 16) | 816 (pdram_timing->tckelcs << 8) | 817 pdram_timing->tcscke); 818 mmio_clrsetbits_32(CTL_REG(i, 58), 0xf, pdram_timing->tzqcke); 819 mmio_clrsetbits_32(CTL_REG(i, 61), 0xffff, pdram_timing->txsnr); 820 mmio_clrsetbits_32(CTL_REG(i, 64), 0xffff << 16, 821 (pdram_timing->tckehcmd << 24) | 822 (pdram_timing->tckelcmd << 16)); 823 mmio_write_32(CTL_REG(i, 65), (pdram_timing->tckelpd << 24) | 824 (pdram_timing->tescke << 16) | 825 (pdram_timing->tsr << 8) | 826 pdram_timing->tckckel); 827 mmio_clrsetbits_32(CTL_REG(i, 66), 0xfff, 828 (pdram_timing->tcmdcke << 8) | 829 pdram_timing->tcsckeh); 830 mmio_clrsetbits_32(CTL_REG(i, 92), (0xff << 24), 831 (pdram_timing->tcksre << 24)); 832 mmio_clrsetbits_32(CTL_REG(i, 93), 0xff, 833 pdram_timing->tcksrx); 834 mmio_clrsetbits_32(CTL_REG(i, 108), (0x1 << 25), 835 (timing_config->dllbp << 25)); 836 mmio_write_32(CTL_REG(i, 125), 837 (pdram_timing->tvrcg_disable << 16) | 838 pdram_timing->tvrcg_enable); 839 mmio_write_32(CTL_REG(i, 126), (pdram_timing->tckfspx << 24) | 840 (pdram_timing->tckfspe << 16) | 841 pdram_timing->tfc_long); 842 mmio_clrsetbits_32(CTL_REG(i, 127), 0xffff, 843 pdram_timing->tvref_long); 844 mmio_clrsetbits_32(CTL_REG(i, 134), 0xffff << 16, 845 pdram_timing->mr[0] << 16); 846 mmio_write_32(CTL_REG(i, 135), (pdram_timing->mr[2] << 16) | 847 pdram_timing->mr[1]); 848 mmio_clrsetbits_32(CTL_REG(i, 138), 0xffff << 16, 849 pdram_timing->mr[3] << 16); 850 mmio_clrsetbits_32(CTL_REG(i, 140), 0xff, pdram_timing->mr11); 851 mmio_clrsetbits_32(CTL_REG(i, 148), 0xffff << 16, 852 pdram_timing->mr[0] << 16); 853 mmio_write_32(CTL_REG(i, 149), (pdram_timing->mr[2] << 16) | 854 pdram_timing->mr[1]); 855 mmio_clrsetbits_32(CTL_REG(i, 152), 0xffff << 16, 856 pdram_timing->mr[3] << 16); 857 mmio_clrsetbits_32(CTL_REG(i, 154), 0xff, pdram_timing->mr11); 858 if (timing_config->dram_type == LPDDR4) { 859 mmio_clrsetbits_32(CTL_REG(i, 141), 0xffff, 860 pdram_timing->mr12); 861 mmio_clrsetbits_32(CTL_REG(i, 143), 0xffff, 862 pdram_timing->mr14); 863 mmio_clrsetbits_32(CTL_REG(i, 146), 0xffff, 864 pdram_timing->mr22); 865 mmio_clrsetbits_32(CTL_REG(i, 155), 0xffff, 866 pdram_timing->mr12); 867 mmio_clrsetbits_32(CTL_REG(i, 157), 0xffff, 868 pdram_timing->mr14); 869 mmio_clrsetbits_32(CTL_REG(i, 160), 0xffff, 870 pdram_timing->mr22); 871 } 872 mmio_write_32(CTL_REG(i, 182), 873 ((pdram_timing->tzqinit / 2) << 16) | 874 pdram_timing->tzqinit); 875 mmio_write_32(CTL_REG(i, 183), (pdram_timing->tzqcal << 16) | 876 pdram_timing->tzqcs); 877 mmio_clrsetbits_32(CTL_REG(i, 184), 0x3f, pdram_timing->tzqlat); 878 mmio_clrsetbits_32(CTL_REG(i, 188), 0xfff, 879 pdram_timing->tzqreset); 880 mmio_clrsetbits_32(CTL_REG(i, 212), 0xff << 16, 881 pdram_timing->todton << 16); 882 883 if (timing_config->odt) { 884 mmio_setbits_32(CTL_REG(i, 213), (1 << 24)); 885 if (timing_config->freq < 400) 886 tmp = 4 << 24; 887 else 888 tmp = 8 << 24; 889 } else { 890 mmio_clrbits_32(CTL_REG(i, 213), (1 << 24)); 891 tmp = 2 << 24; 892 } 893 mmio_clrsetbits_32(CTL_REG(i, 217), 0x1f << 24, tmp); 894 mmio_clrsetbits_32(CTL_REG(i, 221), 0xf << 24, 895 (pdram_timing->tdqsck_max << 24)); 896 mmio_clrsetbits_32(CTL_REG(i, 222), 0x3, pdram_timing->tdqsck); 897 mmio_clrsetbits_32(CTL_REG(i, 291), 0xffff, 898 (get_wrlat_adj(timing_config->dram_type, 899 pdram_timing->cwl) << 8) | 900 get_rdlat_adj(timing_config->dram_type, 901 pdram_timing->cl)); 902 903 mmio_clrsetbits_32(CTL_REG(i, 84), 0xffff, 904 (4 * pdram_timing->trefi) & 0xffff); 905 906 mmio_clrsetbits_32(CTL_REG(i, 84), 0xffff << 16, 907 ((2 * pdram_timing->trefi) & 0xffff) << 16); 908 909 if ((timing_config->dram_type == LPDDR3) || 910 (timing_config->dram_type == LPDDR4)) { 911 tmp = get_pi_wrlat(pdram_timing, timing_config); 912 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 913 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 914 } else { 915 tmp = 0; 916 } 917 mmio_clrsetbits_32(CTL_REG(i, 214), 0x3f << 24, 918 (tmp & 0x3f) << 24); 919 920 if ((timing_config->dram_type == LPDDR3) || 921 (timing_config->dram_type == LPDDR4)) { 922 /* min_rl_preamble = cl + TDQSCK_MIN - 1 */ 923 tmp = pdram_timing->cl + 924 get_pi_todtoff_min(pdram_timing, timing_config); 925 tmp--; 926 /* todtoff_max */ 927 tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); 928 tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; 929 } else { 930 tmp = pdram_timing->cl - pdram_timing->cwl; 931 } 932 mmio_clrsetbits_32(CTL_REG(i, 215), 0x3f << 16, 933 (tmp & 0x3f) << 16); 934 935 mmio_clrsetbits_32(CTL_REG(i, 275), 0xff << 24, 936 (get_pi_tdfi_phy_rdlat(pdram_timing, 937 timing_config) & 938 0xff) << 24); 939 940 mmio_clrsetbits_32(CTL_REG(i, 284), 0xffff << 16, 941 ((2 * pdram_timing->trefi) & 0xffff) << 16); 942 943 mmio_clrsetbits_32(CTL_REG(i, 289), 0xffff, 944 (2 * pdram_timing->trefi) & 0xffff); 945 946 mmio_write_32(CTL_REG(i, 290), 20 * pdram_timing->trefi); 947 948 /* CTL_309 TDFI_CALVL_CAPTURE_F1:RW:16:10 */ 949 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 950 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 951 tmp1++; 952 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 953 mmio_clrsetbits_32(CTL_REG(i, 309), 0x3ff << 16, tmp << 16); 954 955 /* CTL_309 TDFI_CALVL_CC_F1:RW:0:10 */ 956 tmp = tmp + 18; 957 mmio_clrsetbits_32(CTL_REG(i, 309), 0x3ff, tmp); 958 959 /* CTL_314 TDFI_WRCSLAT_F1:RW:24:8 */ 960 tmp1 = get_pi_wrlat_adj(pdram_timing, timing_config); 961 if (timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) { 962 if (tmp1 == 0) 963 tmp = 0; 964 else if (tmp1 < 5) 965 tmp = tmp1 - 1; 966 else 967 tmp = tmp1 - 5; 968 } else { 969 tmp = tmp1 - 2; 970 } 971 972 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 24, tmp << 24); 973 974 /* CTL_314 TDFI_RDCSLAT_F1:RW:16:8 */ 975 if ((timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) && 976 (pdram_timing->cl >= 5)) 977 tmp = pdram_timing->cl - 5; 978 else 979 tmp = pdram_timing->cl - 2; 980 mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 16, tmp << 16); 981 } 982 } 983 984 static void gen_rk3399_enable_training(uint32_t ch_cnt, uint32_t nmhz) 985 { 986 uint32_t i, tmp; 987 988 if (nmhz <= PHY_DLL_BYPASS_FREQ) 989 tmp = 0; 990 else 991 tmp = 1; 992 993 for (i = 0; i < ch_cnt; i++) { 994 mmio_clrsetbits_32(CTL_REG(i, 305), 1 << 16, tmp << 16); 995 mmio_clrsetbits_32(CTL_REG(i, 71), 1, tmp); 996 mmio_clrsetbits_32(CTL_REG(i, 70), 1 << 8, 1 << 8); 997 } 998 } 999 1000 static void gen_rk3399_disable_training(uint32_t ch_cnt) 1001 { 1002 uint32_t i; 1003 1004 for (i = 0; i < ch_cnt; i++) { 1005 mmio_clrbits_32(CTL_REG(i, 305), 1 << 16); 1006 mmio_clrbits_32(CTL_REG(i, 71), 1); 1007 mmio_clrbits_32(CTL_REG(i, 70), 1 << 8); 1008 } 1009 } 1010 1011 static void gen_rk3399_ctl_params(struct timing_related_config *timing_config, 1012 struct dram_timing_t *pdram_timing, 1013 uint32_t fn) 1014 { 1015 if (fn == 0) 1016 gen_rk3399_ctl_params_f0(timing_config, pdram_timing); 1017 else 1018 gen_rk3399_ctl_params_f1(timing_config, pdram_timing); 1019 } 1020 1021 static void gen_rk3399_pi_params_f0(struct timing_related_config *timing_config, 1022 struct dram_timing_t *pdram_timing) 1023 { 1024 uint32_t tmp, tmp1, tmp2; 1025 uint32_t i; 1026 1027 for (i = 0; i < timing_config->ch_cnt; i++) { 1028 /* PI_02 PI_TDFI_PHYMSTR_MAX_F0:RW:0:32 */ 1029 tmp = 4 * pdram_timing->trefi; 1030 mmio_write_32(PI_REG(i, 2), tmp); 1031 /* PI_03 PI_TDFI_PHYMSTR_RESP_F0:RW:0:16 */ 1032 tmp = 2 * pdram_timing->trefi; 1033 mmio_clrsetbits_32(PI_REG(i, 3), 0xffff, tmp); 1034 /* PI_07 PI_TDFI_PHYUPD_RESP_F0:RW:16:16 */ 1035 mmio_clrsetbits_32(PI_REG(i, 7), 0xffff << 16, tmp << 16); 1036 1037 /* PI_42 PI_TDELAY_RDWR_2_BUS_IDLE_F0:RW:0:8 */ 1038 if (timing_config->dram_type == LPDDR4) 1039 tmp = 2; 1040 else 1041 tmp = 0; 1042 tmp = (pdram_timing->bl / 2) + 4 + 1043 (get_pi_rdlat_adj(pdram_timing) - 2) + tmp + 1044 get_pi_tdfi_phy_rdlat(pdram_timing, timing_config); 1045 mmio_clrsetbits_32(PI_REG(i, 42), 0xff, tmp); 1046 /* PI_43 PI_WRLAT_F0:RW:0:5 */ 1047 if (timing_config->dram_type == LPDDR3) { 1048 tmp = get_pi_wrlat(pdram_timing, timing_config); 1049 mmio_clrsetbits_32(PI_REG(i, 43), 0x1f, tmp); 1050 } 1051 /* PI_43 PI_ADDITIVE_LAT_F0:RW:8:6 */ 1052 mmio_clrsetbits_32(PI_REG(i, 43), 0x3f << 8, 1053 PI_ADD_LATENCY << 8); 1054 1055 /* PI_43 PI_CASLAT_LIN_F0:RW:16:7 */ 1056 mmio_clrsetbits_32(PI_REG(i, 43), 0x7f << 16, 1057 (pdram_timing->cl * 2) << 16); 1058 /* PI_46 PI_TREF_F0:RW:16:16 */ 1059 mmio_clrsetbits_32(PI_REG(i, 46), 0xffff << 16, 1060 pdram_timing->trefi << 16); 1061 /* PI_46 PI_TRFC_F0:RW:0:10 */ 1062 mmio_clrsetbits_32(PI_REG(i, 46), 0x3ff, pdram_timing->trfc); 1063 /* PI_66 PI_TODTL_2CMD_F0:RW:24:8 */ 1064 if (timing_config->dram_type == LPDDR3) { 1065 tmp = get_pi_todtoff_max(pdram_timing, timing_config); 1066 mmio_clrsetbits_32(PI_REG(i, 66), 0xff << 24, 1067 tmp << 24); 1068 } 1069 /* PI_72 PI_WR_TO_ODTH_F0:RW:16:6 */ 1070 if ((timing_config->dram_type == LPDDR3) || 1071 (timing_config->dram_type == LPDDR4)) { 1072 tmp1 = get_pi_wrlat(pdram_timing, timing_config); 1073 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1074 if (tmp1 > tmp2) 1075 tmp = tmp1 - tmp2; 1076 else 1077 tmp = 0; 1078 } else if (timing_config->dram_type == DDR3) { 1079 tmp = 0; 1080 } 1081 mmio_clrsetbits_32(PI_REG(i, 72), 0x3f << 16, tmp << 16); 1082 /* PI_73 PI_RD_TO_ODTH_F0:RW:8:6 */ 1083 if ((timing_config->dram_type == LPDDR3) || 1084 (timing_config->dram_type == LPDDR4)) { 1085 /* min_rl_preamble = cl + TDQSCK_MIN - 1 */ 1086 tmp1 = pdram_timing->cl; 1087 tmp1 += get_pi_todtoff_min(pdram_timing, timing_config); 1088 tmp1--; 1089 /* todtoff_max */ 1090 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1091 if (tmp1 > tmp2) 1092 tmp = tmp1 - tmp2; 1093 else 1094 tmp = 0; 1095 } else if (timing_config->dram_type == DDR3) { 1096 tmp = pdram_timing->cl - pdram_timing->cwl; 1097 } 1098 mmio_clrsetbits_32(PI_REG(i, 73), 0x3f << 8, tmp << 8); 1099 /* PI_89 PI_RDLAT_ADJ_F0:RW:16:8 */ 1100 tmp = get_pi_rdlat_adj(pdram_timing); 1101 mmio_clrsetbits_32(PI_REG(i, 89), 0xff << 16, tmp << 16); 1102 /* PI_90 PI_WRLAT_ADJ_F0:RW:16:8 */ 1103 tmp = get_pi_wrlat_adj(pdram_timing, timing_config); 1104 mmio_clrsetbits_32(PI_REG(i, 90), 0xff << 16, tmp << 16); 1105 /* PI_91 PI_TDFI_WRCSLAT_F0:RW:16:8 */ 1106 tmp1 = tmp; 1107 if (tmp1 == 0) 1108 tmp = 0; 1109 else if (tmp1 < 5) 1110 tmp = tmp1 - 1; 1111 else 1112 tmp = tmp1 - 5; 1113 mmio_clrsetbits_32(PI_REG(i, 91), 0xff << 16, tmp << 16); 1114 /* PI_95 PI_TDFI_CALVL_CAPTURE_F0:RW:16:10 */ 1115 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 1116 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 1117 tmp1++; 1118 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 1119 mmio_clrsetbits_32(PI_REG(i, 95), 0x3ff << 16, tmp << 16); 1120 /* PI_95 PI_TDFI_CALVL_CC_F0:RW:0:10 */ 1121 mmio_clrsetbits_32(PI_REG(i, 95), 0x3ff, tmp + 18); 1122 /* PI_102 PI_TMRZ_F0:RW:8:5 */ 1123 mmio_clrsetbits_32(PI_REG(i, 102), 0x1f << 8, 1124 pdram_timing->tmrz << 8); 1125 /* PI_111 PI_TDFI_CALVL_STROBE_F0:RW:8:4 */ 1126 tmp1 = 2 * 1000 / (1000000 / pdram_timing->mhz); 1127 if ((2 * 1000 % (1000000 / pdram_timing->mhz)) != 0) 1128 tmp1++; 1129 /* pi_tdfi_calvl_strobe=tds_train+5 */ 1130 tmp = tmp1 + 5; 1131 mmio_clrsetbits_32(PI_REG(i, 111), 0xf << 8, tmp << 8); 1132 /* PI_116 PI_TCKEHDQS_F0:RW:16:6 */ 1133 tmp = 10000 / (1000000 / pdram_timing->mhz); 1134 if ((10000 % (1000000 / pdram_timing->mhz)) != 0) 1135 tmp++; 1136 if (pdram_timing->mhz <= 100) 1137 tmp = tmp + 1; 1138 else 1139 tmp = tmp + 8; 1140 mmio_clrsetbits_32(PI_REG(i, 116), 0x3f << 16, tmp << 16); 1141 /* PI_125 PI_MR1_DATA_F0_0:RW+:8:16 */ 1142 mmio_clrsetbits_32(PI_REG(i, 125), 0xffff << 8, 1143 pdram_timing->mr[1] << 8); 1144 /* PI_133 PI_MR1_DATA_F0_1:RW+:0:16 */ 1145 mmio_clrsetbits_32(PI_REG(i, 133), 0xffff, pdram_timing->mr[1]); 1146 /* PI_140 PI_MR1_DATA_F0_2:RW+:16:16 */ 1147 mmio_clrsetbits_32(PI_REG(i, 140), 0xffff << 16, 1148 pdram_timing->mr[1] << 16); 1149 /* PI_148 PI_MR1_DATA_F0_3:RW+:0:16 */ 1150 mmio_clrsetbits_32(PI_REG(i, 148), 0xffff, pdram_timing->mr[1]); 1151 /* PI_126 PI_MR2_DATA_F0_0:RW+:0:16 */ 1152 mmio_clrsetbits_32(PI_REG(i, 126), 0xffff, pdram_timing->mr[2]); 1153 /* PI_133 PI_MR2_DATA_F0_1:RW+:16:16 */ 1154 mmio_clrsetbits_32(PI_REG(i, 133), 0xffff << 16, 1155 pdram_timing->mr[2] << 16); 1156 /* PI_141 PI_MR2_DATA_F0_2:RW+:0:16 */ 1157 mmio_clrsetbits_32(PI_REG(i, 141), 0xffff, pdram_timing->mr[2]); 1158 /* PI_148 PI_MR2_DATA_F0_3:RW+:16:16 */ 1159 mmio_clrsetbits_32(PI_REG(i, 148), 0xffff << 16, 1160 pdram_timing->mr[2] << 16); 1161 /* PI_156 PI_TFC_F0:RW:0:10 */ 1162 mmio_clrsetbits_32(PI_REG(i, 156), 0x3ff, 1163 pdram_timing->tfc_long); 1164 /* PI_158 PI_TWR_F0:RW:24:6 */ 1165 mmio_clrsetbits_32(PI_REG(i, 158), 0x3f << 24, 1166 pdram_timing->twr << 24); 1167 /* PI_158 PI_TWTR_F0:RW:16:6 */ 1168 mmio_clrsetbits_32(PI_REG(i, 158), 0x3f << 16, 1169 pdram_timing->twtr << 16); 1170 /* PI_158 PI_TRCD_F0:RW:8:8 */ 1171 mmio_clrsetbits_32(PI_REG(i, 158), 0xff << 8, 1172 pdram_timing->trcd << 8); 1173 /* PI_158 PI_TRP_F0:RW:0:8 */ 1174 mmio_clrsetbits_32(PI_REG(i, 158), 0xff, pdram_timing->trp); 1175 /* PI_157 PI_TRTP_F0:RW:24:8 */ 1176 mmio_clrsetbits_32(PI_REG(i, 157), 0xff << 24, 1177 pdram_timing->trtp << 24); 1178 /* PI_159 PI_TRAS_MIN_F0:RW:24:8 */ 1179 mmio_clrsetbits_32(PI_REG(i, 159), 0xff << 24, 1180 pdram_timing->tras_min << 24); 1181 /* PI_159 PI_TRAS_MAX_F0:RW:0:17 */ 1182 tmp = pdram_timing->tras_max * 99 / 100; 1183 mmio_clrsetbits_32(PI_REG(i, 159), 0x1ffff, tmp); 1184 /* PI_160 PI_TMRD_F0:RW:16:6 */ 1185 mmio_clrsetbits_32(PI_REG(i, 160), 0x3f << 16, 1186 pdram_timing->tmrd << 16); 1187 /*PI_160 PI_TDQSCK_MAX_F0:RW:0:4 */ 1188 mmio_clrsetbits_32(PI_REG(i, 160), 0xf, 1189 pdram_timing->tdqsck_max); 1190 /* PI_187 PI_TDFI_CTRLUPD_MAX_F0:RW:8:16 */ 1191 mmio_clrsetbits_32(PI_REG(i, 187), 0xffff << 8, 1192 (2 * pdram_timing->trefi) << 8); 1193 /* PI_188 PI_TDFI_CTRLUPD_INTERVAL_F0:RW:0:32 */ 1194 mmio_clrsetbits_32(PI_REG(i, 188), 0xffffffff, 1195 20 * pdram_timing->trefi); 1196 } 1197 } 1198 1199 static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config, 1200 struct dram_timing_t *pdram_timing) 1201 { 1202 uint32_t tmp, tmp1, tmp2; 1203 uint32_t i; 1204 1205 for (i = 0; i < timing_config->ch_cnt; i++) { 1206 /* PI_04 PI_TDFI_PHYMSTR_MAX_F1:RW:0:32 */ 1207 tmp = 4 * pdram_timing->trefi; 1208 mmio_write_32(PI_REG(i, 4), tmp); 1209 /* PI_05 PI_TDFI_PHYMSTR_RESP_F1:RW:0:16 */ 1210 tmp = 2 * pdram_timing->trefi; 1211 mmio_clrsetbits_32(PI_REG(i, 5), 0xffff, tmp); 1212 /* PI_12 PI_TDFI_PHYUPD_RESP_F1:RW:0:16 */ 1213 mmio_clrsetbits_32(PI_REG(i, 12), 0xffff, tmp); 1214 1215 /* PI_42 PI_TDELAY_RDWR_2_BUS_IDLE_F1:RW:8:8 */ 1216 if (timing_config->dram_type == LPDDR4) 1217 tmp = 2; 1218 else 1219 tmp = 0; 1220 tmp = (pdram_timing->bl / 2) + 4 + 1221 (get_pi_rdlat_adj(pdram_timing) - 2) + tmp + 1222 get_pi_tdfi_phy_rdlat(pdram_timing, timing_config); 1223 mmio_clrsetbits_32(PI_REG(i, 42), 0xff << 8, tmp << 8); 1224 /* PI_43 PI_WRLAT_F1:RW:24:5 */ 1225 if (timing_config->dram_type == LPDDR3) { 1226 tmp = get_pi_wrlat(pdram_timing, timing_config); 1227 mmio_clrsetbits_32(PI_REG(i, 43), 0x1f << 24, 1228 tmp << 24); 1229 } 1230 /* PI_44 PI_ADDITIVE_LAT_F1:RW:0:6 */ 1231 mmio_clrsetbits_32(PI_REG(i, 44), 0x3f, PI_ADD_LATENCY); 1232 /* PI_44 PI_CASLAT_LIN_F1:RW:8:7:=0x18 */ 1233 mmio_clrsetbits_32(PI_REG(i, 44), 0x7f << 8, 1234 (pdram_timing->cl * 2) << 8); 1235 /* PI_47 PI_TREF_F1:RW:16:16 */ 1236 mmio_clrsetbits_32(PI_REG(i, 47), 0xffff << 16, 1237 pdram_timing->trefi << 16); 1238 /* PI_47 PI_TRFC_F1:RW:0:10 */ 1239 mmio_clrsetbits_32(PI_REG(i, 47), 0x3ff, pdram_timing->trfc); 1240 /* PI_67 PI_TODTL_2CMD_F1:RW:8:8 */ 1241 if (timing_config->dram_type == LPDDR3) { 1242 tmp = get_pi_todtoff_max(pdram_timing, timing_config); 1243 mmio_clrsetbits_32(PI_REG(i, 67), 0xff << 8, tmp << 8); 1244 } 1245 /* PI_72 PI_WR_TO_ODTH_F1:RW:24:6 */ 1246 if ((timing_config->dram_type == LPDDR3) || 1247 (timing_config->dram_type == LPDDR4)) { 1248 tmp1 = get_pi_wrlat(pdram_timing, timing_config); 1249 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1250 if (tmp1 > tmp2) 1251 tmp = tmp1 - tmp2; 1252 else 1253 tmp = 0; 1254 } else if (timing_config->dram_type == DDR3) { 1255 tmp = 0; 1256 } 1257 mmio_clrsetbits_32(PI_REG(i, 72), 0x3f << 24, tmp << 24); 1258 /* PI_73 PI_RD_TO_ODTH_F1:RW:16:6 */ 1259 if ((timing_config->dram_type == LPDDR3) || 1260 (timing_config->dram_type == LPDDR4)) { 1261 /* min_rl_preamble = cl + TDQSCK_MIN - 1 */ 1262 tmp1 = pdram_timing->cl + 1263 get_pi_todtoff_min(pdram_timing, timing_config); 1264 tmp1--; 1265 /* todtoff_max */ 1266 tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); 1267 if (tmp1 > tmp2) 1268 tmp = tmp1 - tmp2; 1269 else 1270 tmp = 0; 1271 } else if (timing_config->dram_type == DDR3) 1272 tmp = pdram_timing->cl - pdram_timing->cwl; 1273 1274 mmio_clrsetbits_32(PI_REG(i, 73), 0x3f << 16, tmp << 16); 1275 /*P I_89 PI_RDLAT_ADJ_F1:RW:24:8 */ 1276 tmp = get_pi_rdlat_adj(pdram_timing); 1277 mmio_clrsetbits_32(PI_REG(i, 89), 0xff << 24, tmp << 24); 1278 /* PI_90 PI_WRLAT_ADJ_F1:RW:24:8 */ 1279 tmp = get_pi_wrlat_adj(pdram_timing, timing_config); 1280 mmio_clrsetbits_32(PI_REG(i, 90), 0xff << 24, tmp << 24); 1281 /* PI_91 PI_TDFI_WRCSLAT_F1:RW:24:8 */ 1282 tmp1 = tmp; 1283 if (tmp1 == 0) 1284 tmp = 0; 1285 else if (tmp1 < 5) 1286 tmp = tmp1 - 1; 1287 else 1288 tmp = tmp1 - 5; 1289 mmio_clrsetbits_32(PI_REG(i, 91), 0xff << 24, tmp << 24); 1290 /*PI_96 PI_TDFI_CALVL_CAPTURE_F1:RW:16:10 */ 1291 /* tadr=20ns */ 1292 tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; 1293 if ((20000 % (1000000 / pdram_timing->mhz)) != 0) 1294 tmp1++; 1295 tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; 1296 mmio_clrsetbits_32(PI_REG(i, 96), 0x3ff << 16, tmp << 16); 1297 /* PI_96 PI_TDFI_CALVL_CC_F1:RW:0:10 */ 1298 tmp = tmp + 18; 1299 mmio_clrsetbits_32(PI_REG(i, 96), 0x3ff, tmp); 1300 /*PI_103 PI_TMRZ_F1:RW:0:5 */ 1301 mmio_clrsetbits_32(PI_REG(i, 103), 0x1f, pdram_timing->tmrz); 1302 /*PI_111 PI_TDFI_CALVL_STROBE_F1:RW:16:4 */ 1303 /* tds_train=ceil(2/ns) */ 1304 tmp1 = 2 * 1000 / (1000000 / pdram_timing->mhz); 1305 if ((2 * 1000 % (1000000 / pdram_timing->mhz)) != 0) 1306 tmp1++; 1307 /* pi_tdfi_calvl_strobe=tds_train+5 */ 1308 tmp = tmp1 + 5; 1309 mmio_clrsetbits_32(PI_REG(i, 111), 0xf << 16, 1310 tmp << 16); 1311 /* PI_116 PI_TCKEHDQS_F1:RW:24:6 */ 1312 tmp = 10000 / (1000000 / pdram_timing->mhz); 1313 if ((10000 % (1000000 / pdram_timing->mhz)) != 0) 1314 tmp++; 1315 if (pdram_timing->mhz <= 100) 1316 tmp = tmp + 1; 1317 else 1318 tmp = tmp + 8; 1319 mmio_clrsetbits_32(PI_REG(i, 116), 0x3f << 24, 1320 tmp << 24); 1321 /* PI_128 PI_MR1_DATA_F1_0:RW+:0:16 */ 1322 mmio_clrsetbits_32(PI_REG(i, 128), 0xffff, pdram_timing->mr[1]); 1323 /* PI_135 PI_MR1_DATA_F1_1:RW+:8:16 */ 1324 mmio_clrsetbits_32(PI_REG(i, 135), 0xffff << 8, 1325 pdram_timing->mr[1] << 8); 1326 /* PI_143 PI_MR1_DATA_F1_2:RW+:0:16 */ 1327 mmio_clrsetbits_32(PI_REG(i, 143), 0xffff, pdram_timing->mr[1]); 1328 /* PI_150 PI_MR1_DATA_F1_3:RW+:8:16 */ 1329 mmio_clrsetbits_32(PI_REG(i, 150), 0xffff << 8, 1330 pdram_timing->mr[1] << 8); 1331 /* PI_128 PI_MR2_DATA_F1_0:RW+:16:16 */ 1332 mmio_clrsetbits_32(PI_REG(i, 128), 0xffff << 16, 1333 pdram_timing->mr[2] << 16); 1334 /* PI_136 PI_MR2_DATA_F1_1:RW+:0:16 */ 1335 mmio_clrsetbits_32(PI_REG(i, 136), 0xffff, pdram_timing->mr[2]); 1336 /* PI_143 PI_MR2_DATA_F1_2:RW+:16:16 */ 1337 mmio_clrsetbits_32(PI_REG(i, 143), 0xffff << 16, 1338 pdram_timing->mr[2] << 16); 1339 /* PI_151 PI_MR2_DATA_F1_3:RW+:0:16 */ 1340 mmio_clrsetbits_32(PI_REG(i, 151), 0xffff, pdram_timing->mr[2]); 1341 /* PI_156 PI_TFC_F1:RW:16:10 */ 1342 mmio_clrsetbits_32(PI_REG(i, 156), 0x3ff << 16, 1343 pdram_timing->tfc_long << 16); 1344 /* PI_162 PI_TWR_F1:RW:8:6 */ 1345 mmio_clrsetbits_32(PI_REG(i, 162), 0x3f << 8, 1346 pdram_timing->twr << 8); 1347 /* PI_162 PI_TWTR_F1:RW:0:6 */ 1348 mmio_clrsetbits_32(PI_REG(i, 162), 0x3f, pdram_timing->twtr); 1349 /* PI_161 PI_TRCD_F1:RW:24:8 */ 1350 mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 24, 1351 pdram_timing->trcd << 24); 1352 /* PI_161 PI_TRP_F1:RW:16:8 */ 1353 mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 16, 1354 pdram_timing->trp << 16); 1355 /* PI_161 PI_TRTP_F1:RW:8:8 */ 1356 mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 8, 1357 pdram_timing->trtp << 8); 1358 /* PI_163 PI_TRAS_MIN_F1:RW:24:8 */ 1359 mmio_clrsetbits_32(PI_REG(i, 163), 0xff << 24, 1360 pdram_timing->tras_min << 24); 1361 /* PI_163 PI_TRAS_MAX_F1:RW:0:17 */ 1362 mmio_clrsetbits_32(PI_REG(i, 163), 0x1ffff, 1363 pdram_timing->tras_max * 99 / 100); 1364 /* PI_164 PI_TMRD_F1:RW:16:6 */ 1365 mmio_clrsetbits_32(PI_REG(i, 164), 0x3f << 16, 1366 pdram_timing->tmrd << 16); 1367 /* PI_164 PI_TDQSCK_MAX_F1:RW:0:4 */ 1368 mmio_clrsetbits_32(PI_REG(i, 164), 0xf, 1369 pdram_timing->tdqsck_max); 1370 /* PI_189 PI_TDFI_CTRLUPD_MAX_F1:RW:0:16 */ 1371 mmio_clrsetbits_32(PI_REG(i, 189), 0xffff, 1372 2 * pdram_timing->trefi); 1373 /* PI_190 PI_TDFI_CTRLUPD_INTERVAL_F1:RW:0:32 */ 1374 mmio_clrsetbits_32(PI_REG(i, 190), 0xffffffff, 1375 20 * pdram_timing->trefi); 1376 } 1377 } 1378 1379 static void gen_rk3399_pi_params(struct timing_related_config *timing_config, 1380 struct dram_timing_t *pdram_timing, 1381 uint32_t fn) 1382 { 1383 if (fn == 0) 1384 gen_rk3399_pi_params_f0(timing_config, pdram_timing); 1385 else 1386 gen_rk3399_pi_params_f1(timing_config, pdram_timing); 1387 } 1388 1389 static void gen_rk3399_set_odt(uint32_t odt_en) 1390 { 1391 uint32_t drv_odt_val; 1392 uint32_t i; 1393 1394 for (i = 0; i < rk3399_dram_status.timing_config.ch_cnt; i++) { 1395 drv_odt_val = (odt_en | (0 << 1) | (0 << 2)) << 16; 1396 mmio_clrsetbits_32(PHY_REG(i, 5), 0x7 << 16, drv_odt_val); 1397 mmio_clrsetbits_32(PHY_REG(i, 133), 0x7 << 16, drv_odt_val); 1398 mmio_clrsetbits_32(PHY_REG(i, 261), 0x7 << 16, drv_odt_val); 1399 mmio_clrsetbits_32(PHY_REG(i, 389), 0x7 << 16, drv_odt_val); 1400 drv_odt_val = (odt_en | (0 << 1) | (0 << 2)) << 24; 1401 mmio_clrsetbits_32(PHY_REG(i, 6), 0x7 << 24, drv_odt_val); 1402 mmio_clrsetbits_32(PHY_REG(i, 134), 0x7 << 24, drv_odt_val); 1403 mmio_clrsetbits_32(PHY_REG(i, 262), 0x7 << 24, drv_odt_val); 1404 mmio_clrsetbits_32(PHY_REG(i, 390), 0x7 << 24, drv_odt_val); 1405 } 1406 } 1407 1408 static void gen_rk3399_phy_dll_bypass(uint32_t mhz, uint32_t ch, 1409 uint32_t index, uint32_t dram_type) 1410 { 1411 uint32_t sw_master_mode = 0; 1412 uint32_t rddqs_gate_delay, rddqs_latency, total_delay; 1413 uint32_t i; 1414 1415 if (dram_type == DDR3) 1416 total_delay = PI_PAD_DELAY_PS_VALUE; 1417 else if (dram_type == LPDDR3) 1418 total_delay = PI_PAD_DELAY_PS_VALUE + 2500; 1419 else 1420 total_delay = PI_PAD_DELAY_PS_VALUE + 1500; 1421 /* total_delay + 0.55tck */ 1422 total_delay += (55 * 10000)/mhz; 1423 rddqs_latency = total_delay * mhz / 1000000; 1424 total_delay -= rddqs_latency * 1000000 / mhz; 1425 rddqs_gate_delay = total_delay * 0x200 * mhz / 1000000; 1426 if (mhz <= PHY_DLL_BYPASS_FREQ) { 1427 sw_master_mode = 0xc; 1428 mmio_setbits_32(PHY_REG(ch, 514), 1); 1429 mmio_setbits_32(PHY_REG(ch, 642), 1); 1430 mmio_setbits_32(PHY_REG(ch, 770), 1); 1431 1432 /* setting bypass mode slave delay */ 1433 for (i = 0; i < 4; i++) { 1434 /* wr dq delay = -180deg + (0x60 / 4) * 20ps */ 1435 mmio_clrsetbits_32(PHY_REG(ch, 1 + 128 * i), 0x7ff << 8, 1436 0x4a0 << 8); 1437 /* rd dqs/dq delay = (0x60 / 4) * 20ps */ 1438 mmio_clrsetbits_32(PHY_REG(ch, 11 + 128 * i), 0x3ff, 1439 0xa0); 1440 /* rd rddqs_gate delay */ 1441 mmio_clrsetbits_32(PHY_REG(ch, 2 + 128 * i), 0x3ff, 1442 rddqs_gate_delay); 1443 mmio_clrsetbits_32(PHY_REG(ch, 78 + 128 * i), 0xf, 1444 rddqs_latency); 1445 } 1446 for (i = 0; i < 3; i++) 1447 /* adr delay */ 1448 mmio_clrsetbits_32(PHY_REG(ch, 513 + 128 * i), 1449 0x7ff << 16, 0x80 << 16); 1450 1451 if ((mmio_read_32(PHY_REG(ch, 86)) & 0xc00) == 0) { 1452 /* 1453 * old status is normal mode, 1454 * and saving the wrdqs slave delay 1455 */ 1456 for (i = 0; i < 4; i++) { 1457 /* save and clear wr dqs slave delay */ 1458 wrdqs_delay_val[ch][index][i] = 0x3ff & 1459 (mmio_read_32(PHY_REG(ch, 63 + i * 128)) 1460 >> 16); 1461 mmio_clrsetbits_32(PHY_REG(ch, 63 + i * 128), 1462 0x03ff << 16, 0 << 16); 1463 /* 1464 * in normal mode the cmd may delay 1cycle by 1465 * wrlvl and in bypass mode making dqs also 1466 * delay 1cycle. 1467 */ 1468 mmio_clrsetbits_32(PHY_REG(ch, 78 + i * 128), 1469 0x07 << 8, 0x1 << 8); 1470 } 1471 } 1472 } else if (mmio_read_32(PHY_REG(ch, 86)) & 0xc00) { 1473 /* old status is bypass mode and restore wrlvl resume */ 1474 for (i = 0; i < 4; i++) { 1475 mmio_clrsetbits_32(PHY_REG(ch, 63 + i * 128), 1476 0x03ff << 16, 1477 (wrdqs_delay_val[ch][index][i] & 1478 0x3ff) << 16); 1479 /* resume phy_write_path_lat_add */ 1480 mmio_clrbits_32(PHY_REG(ch, 78 + i * 128), 0x07 << 8); 1481 } 1482 } 1483 1484 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ 1485 mmio_clrsetbits_32(PHY_REG(ch, 86), 0xf << 8, sw_master_mode << 8); 1486 mmio_clrsetbits_32(PHY_REG(ch, 214), 0xf << 8, sw_master_mode << 8); 1487 mmio_clrsetbits_32(PHY_REG(ch, 342), 0xf << 8, sw_master_mode << 8); 1488 mmio_clrsetbits_32(PHY_REG(ch, 470), 0xf << 8, sw_master_mode << 8); 1489 1490 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ 1491 mmio_clrsetbits_32(PHY_REG(ch, 547), 0xf << 16, sw_master_mode << 16); 1492 mmio_clrsetbits_32(PHY_REG(ch, 675), 0xf << 16, sw_master_mode << 16); 1493 mmio_clrsetbits_32(PHY_REG(ch, 803), 0xf << 16, sw_master_mode << 16); 1494 } 1495 1496 static void gen_rk3399_phy_params(struct timing_related_config *timing_config, 1497 struct drv_odt_lp_config *drv_config, 1498 struct dram_timing_t *pdram_timing, 1499 uint32_t fn) 1500 { 1501 uint32_t tmp, i, div, j; 1502 uint32_t mem_delay_ps, pad_delay_ps, total_delay_ps, delay_frac_ps; 1503 uint32_t trpre_min_ps, gate_delay_ps, gate_delay_frac_ps; 1504 uint32_t ie_enable, tsel_enable, cas_lat, rddata_en_ie_dly, tsel_adder; 1505 uint32_t extra_adder, delta, hs_offset; 1506 1507 for (i = 0; i < timing_config->ch_cnt; i++) { 1508 1509 pad_delay_ps = PI_PAD_DELAY_PS_VALUE; 1510 ie_enable = PI_IE_ENABLE_VALUE; 1511 tsel_enable = PI_TSEL_ENABLE_VALUE; 1512 1513 mmio_clrsetbits_32(PHY_REG(i, 896), (0x3 << 8) | 1, fn << 8); 1514 1515 /* PHY_LOW_FREQ_SEL */ 1516 /* DENALI_PHY_913 1bit offset_0 */ 1517 if (timing_config->freq > 400) 1518 mmio_clrbits_32(PHY_REG(i, 913), 1); 1519 else 1520 mmio_setbits_32(PHY_REG(i, 913), 1); 1521 1522 /* PHY_RPTR_UPDATE_x */ 1523 /* DENALI_PHY_87/215/343/471 4bit offset_16 */ 1524 tmp = 2500 / (1000000 / pdram_timing->mhz) + 3; 1525 if ((2500 % (1000000 / pdram_timing->mhz)) != 0) 1526 tmp++; 1527 mmio_clrsetbits_32(PHY_REG(i, 87), 0xf << 16, tmp << 16); 1528 mmio_clrsetbits_32(PHY_REG(i, 215), 0xf << 16, tmp << 16); 1529 mmio_clrsetbits_32(PHY_REG(i, 343), 0xf << 16, tmp << 16); 1530 mmio_clrsetbits_32(PHY_REG(i, 471), 0xf << 16, tmp << 16); 1531 1532 /* PHY_PLL_CTRL */ 1533 /* DENALI_PHY_911 13bits offset_0 */ 1534 /* PHY_LP4_BOOT_PLL_CTRL */ 1535 /* DENALI_PHY_919 13bits offset_0 */ 1536 tmp = (1 << 12) | (2 << 7) | (1 << 1); 1537 mmio_clrsetbits_32(PHY_REG(i, 911), 0x1fff, tmp); 1538 mmio_clrsetbits_32(PHY_REG(i, 919), 0x1fff, tmp); 1539 1540 /* PHY_PLL_CTRL_CA */ 1541 /* DENALI_PHY_911 13bits offset_16 */ 1542 /* PHY_LP4_BOOT_PLL_CTRL_CA */ 1543 /* DENALI_PHY_919 13bits offset_16 */ 1544 tmp = (2 << 7) | (1 << 5) | (1 << 1); 1545 mmio_clrsetbits_32(PHY_REG(i, 911), 0x1fff << 16, tmp << 16); 1546 mmio_clrsetbits_32(PHY_REG(i, 919), 0x1fff << 16, tmp << 16); 1547 1548 /* PHY_TCKSRE_WAIT */ 1549 /* DENALI_PHY_922 4bits offset_24 */ 1550 if (pdram_timing->mhz <= 400) 1551 tmp = 1; 1552 else if (pdram_timing->mhz <= 800) 1553 tmp = 3; 1554 else if (pdram_timing->mhz <= 1000) 1555 tmp = 4; 1556 else 1557 tmp = 5; 1558 mmio_clrsetbits_32(PHY_REG(i, 922), 0xf << 24, tmp << 24); 1559 /* PHY_CAL_CLK_SELECT_0:RW8:3 */ 1560 div = pdram_timing->mhz / (2 * 20); 1561 for (j = 2, tmp = 1; j <= 128; j <<= 1, tmp++) { 1562 if (div < j) 1563 break; 1564 } 1565 mmio_clrsetbits_32(PHY_REG(i, 947), 0x7 << 8, tmp << 8); 1566 1567 if (timing_config->dram_type == DDR3) { 1568 mem_delay_ps = 0; 1569 trpre_min_ps = 1000; 1570 } else if (timing_config->dram_type == LPDDR4) { 1571 mem_delay_ps = 1500; 1572 trpre_min_ps = 900; 1573 } else if (timing_config->dram_type == LPDDR3) { 1574 mem_delay_ps = 2500; 1575 trpre_min_ps = 900; 1576 } else { 1577 ERROR("gen_rk3399_phy_params:dramtype unsupport\n"); 1578 return; 1579 } 1580 total_delay_ps = mem_delay_ps + pad_delay_ps; 1581 delay_frac_ps = 1000 * total_delay_ps / 1582 (1000000 / pdram_timing->mhz); 1583 gate_delay_ps = delay_frac_ps + 1000 - (trpre_min_ps / 2); 1584 gate_delay_frac_ps = gate_delay_ps % 1000; 1585 tmp = gate_delay_frac_ps * 0x200 / 1000; 1586 /* PHY_RDDQS_GATE_SLAVE_DELAY */ 1587 /* DENALI_PHY_77/205/333/461 10bits offset_16 */ 1588 mmio_clrsetbits_32(PHY_REG(i, 77), 0x2ff << 16, tmp << 16); 1589 mmio_clrsetbits_32(PHY_REG(i, 205), 0x2ff << 16, tmp << 16); 1590 mmio_clrsetbits_32(PHY_REG(i, 333), 0x2ff << 16, tmp << 16); 1591 mmio_clrsetbits_32(PHY_REG(i, 461), 0x2ff << 16, tmp << 16); 1592 1593 tmp = gate_delay_ps / 1000; 1594 /* PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST */ 1595 /* DENALI_PHY_10/138/266/394 4bit offset_0 */ 1596 mmio_clrsetbits_32(PHY_REG(i, 10), 0xf, tmp); 1597 mmio_clrsetbits_32(PHY_REG(i, 138), 0xf, tmp); 1598 mmio_clrsetbits_32(PHY_REG(i, 266), 0xf, tmp); 1599 mmio_clrsetbits_32(PHY_REG(i, 394), 0xf, tmp); 1600 /* PHY_GTLVL_LAT_ADJ_START */ 1601 /* DENALI_PHY_80/208/336/464 4bits offset_16 */ 1602 tmp = delay_frac_ps / 1000; 1603 mmio_clrsetbits_32(PHY_REG(i, 80), 0xf << 16, tmp << 16); 1604 mmio_clrsetbits_32(PHY_REG(i, 208), 0xf << 16, tmp << 16); 1605 mmio_clrsetbits_32(PHY_REG(i, 336), 0xf << 16, tmp << 16); 1606 mmio_clrsetbits_32(PHY_REG(i, 464), 0xf << 16, tmp << 16); 1607 1608 cas_lat = pdram_timing->cl + PI_ADD_LATENCY; 1609 rddata_en_ie_dly = ie_enable / (1000000 / pdram_timing->mhz); 1610 if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) 1611 rddata_en_ie_dly++; 1612 rddata_en_ie_dly = rddata_en_ie_dly - 1; 1613 tsel_adder = tsel_enable / (1000000 / pdram_timing->mhz); 1614 if ((tsel_enable % (1000000 / pdram_timing->mhz)) != 0) 1615 tsel_adder++; 1616 if (rddata_en_ie_dly > tsel_adder) 1617 extra_adder = rddata_en_ie_dly - tsel_adder; 1618 else 1619 extra_adder = 0; 1620 delta = cas_lat - rddata_en_ie_dly; 1621 if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) 1622 hs_offset = 2; 1623 else 1624 hs_offset = 1; 1625 if (rddata_en_ie_dly > (cas_lat - 1 - hs_offset)) 1626 tmp = 0; 1627 else if ((delta == 2) || (delta == 1)) 1628 tmp = rddata_en_ie_dly - 0 - extra_adder; 1629 else 1630 tmp = extra_adder; 1631 /* PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY */ 1632 /* DENALI_PHY_9/137/265/393 4bit offset_16 */ 1633 mmio_clrsetbits_32(PHY_REG(i, 9), 0xf << 16, tmp << 16); 1634 mmio_clrsetbits_32(PHY_REG(i, 137), 0xf << 16, tmp << 16); 1635 mmio_clrsetbits_32(PHY_REG(i, 265), 0xf << 16, tmp << 16); 1636 mmio_clrsetbits_32(PHY_REG(i, 393), 0xf << 16, tmp << 16); 1637 /* PHY_RDDATA_EN_TSEL_DLY */ 1638 /* DENALI_PHY_86/214/342/470 4bit offset_0 */ 1639 mmio_clrsetbits_32(PHY_REG(i, 86), 0xf, tmp); 1640 mmio_clrsetbits_32(PHY_REG(i, 214), 0xf, tmp); 1641 mmio_clrsetbits_32(PHY_REG(i, 342), 0xf, tmp); 1642 mmio_clrsetbits_32(PHY_REG(i, 470), 0xf, tmp); 1643 1644 if (tsel_adder > rddata_en_ie_dly) 1645 extra_adder = tsel_adder - rddata_en_ie_dly; 1646 else 1647 extra_adder = 0; 1648 if (rddata_en_ie_dly > (cas_lat - 1 - hs_offset)) 1649 tmp = tsel_adder; 1650 else 1651 tmp = rddata_en_ie_dly - 0 + extra_adder; 1652 /* PHY_LP4_BOOT_RDDATA_EN_DLY */ 1653 /* DENALI_PHY_9/137/265/393 4bit offset_8 */ 1654 mmio_clrsetbits_32(PHY_REG(i, 9), 0xf << 8, tmp << 8); 1655 mmio_clrsetbits_32(PHY_REG(i, 137), 0xf << 8, tmp << 8); 1656 mmio_clrsetbits_32(PHY_REG(i, 265), 0xf << 8, tmp << 8); 1657 mmio_clrsetbits_32(PHY_REG(i, 393), 0xf << 8, tmp << 8); 1658 /* PHY_RDDATA_EN_DLY */ 1659 /* DENALI_PHY_85/213/341/469 4bit offset_24 */ 1660 mmio_clrsetbits_32(PHY_REG(i, 85), 0xf << 24, tmp << 24); 1661 mmio_clrsetbits_32(PHY_REG(i, 213), 0xf << 24, tmp << 24); 1662 mmio_clrsetbits_32(PHY_REG(i, 341), 0xf << 24, tmp << 24); 1663 mmio_clrsetbits_32(PHY_REG(i, 469), 0xf << 24, tmp << 24); 1664 1665 if (pdram_timing->mhz <= ENPER_CS_TRAINING_FREQ) { 1666 /* 1667 * Note:Per-CS Training is not compatible at speeds 1668 * under 533 MHz. If the PHY is running at a speed 1669 * less than 533MHz, all phy_per_cs_training_en_X 1670 * parameters must be cleared to 0. 1671 */ 1672 1673 /*DENALI_PHY_84/212/340/468 1bit offset_16 */ 1674 mmio_clrbits_32(PHY_REG(i, 84), 0x1 << 16); 1675 mmio_clrbits_32(PHY_REG(i, 212), 0x1 << 16); 1676 mmio_clrbits_32(PHY_REG(i, 340), 0x1 << 16); 1677 mmio_clrbits_32(PHY_REG(i, 468), 0x1 << 16); 1678 } else { 1679 mmio_setbits_32(PHY_REG(i, 84), 0x1 << 16); 1680 mmio_setbits_32(PHY_REG(i, 212), 0x1 << 16); 1681 mmio_setbits_32(PHY_REG(i, 340), 0x1 << 16); 1682 mmio_setbits_32(PHY_REG(i, 468), 0x1 << 16); 1683 } 1684 gen_rk3399_phy_dll_bypass(pdram_timing->mhz, i, fn, 1685 timing_config->dram_type); 1686 } 1687 } 1688 1689 static int to_get_clk_index(unsigned int mhz) 1690 { 1691 int pll_cnt, i; 1692 1693 pll_cnt = ARRAY_SIZE(dpll_rates_table); 1694 1695 /* Assumming rate_table is in descending order */ 1696 for (i = 0; i < pll_cnt; i++) { 1697 if (mhz >= dpll_rates_table[i].mhz) 1698 break; 1699 } 1700 1701 /* if mhz lower than lowest frequency in table, use lowest frequency */ 1702 if (i == pll_cnt) 1703 i = pll_cnt - 1; 1704 1705 return i; 1706 } 1707 1708 uint32_t ddr_get_rate(void) 1709 { 1710 uint32_t refdiv, postdiv1, fbdiv, postdiv2; 1711 1712 refdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) & 0x3f; 1713 fbdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 0)) & 0xfff; 1714 postdiv1 = 1715 (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 8) & 0x7; 1716 postdiv2 = 1717 (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 12) & 0x7; 1718 1719 return (24 / refdiv * fbdiv / postdiv1 / postdiv2) * 1000 * 1000; 1720 } 1721 1722 /* 1723 * return: bit12: channel 1, external self-refresh 1724 * bit11: channel 1, stdby_mode 1725 * bit10: channel 1, self-refresh with controller and memory clock gate 1726 * bit9: channel 1, self-refresh 1727 * bit8: channel 1, power-down 1728 * 1729 * bit4: channel 1, external self-refresh 1730 * bit3: channel 0, stdby_mode 1731 * bit2: channel 0, self-refresh with controller and memory clock gate 1732 * bit1: channel 0, self-refresh 1733 * bit0: channel 0, power-down 1734 */ 1735 uint32_t exit_low_power(void) 1736 { 1737 uint32_t low_power = 0; 1738 uint32_t channel_mask; 1739 uint32_t tmp, i; 1740 1741 channel_mask = (mmio_read_32(PMUGRF_BASE + PMUGRF_OSREG(2)) >> 28) & 1742 0x3; 1743 for (i = 0; i < 2; i++) { 1744 if (!(channel_mask & (1 << i))) 1745 continue; 1746 1747 /* exit stdby mode */ 1748 mmio_write_32(CIC_BASE + CIC_CTRL1, 1749 (1 << (i + 16)) | (0 << i)); 1750 /* exit external self-refresh */ 1751 tmp = i ? 12 : 8; 1752 low_power |= ((mmio_read_32(PMU_BASE + PMU_SFT_CON) >> tmp) & 1753 0x1) << (4 + 8 * i); 1754 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, 1 << tmp); 1755 while (!(mmio_read_32(PMU_BASE + PMU_DDR_SREF_ST) & (1 << i))) 1756 ; 1757 /* exit auto low-power */ 1758 mmio_clrbits_32(CTL_REG(i, 101), 0x7); 1759 /* lp_cmd to exit */ 1760 if (((mmio_read_32(CTL_REG(i, 100)) >> 24) & 0x7f) != 1761 0x40) { 1762 while (mmio_read_32(CTL_REG(i, 200)) & 0x1) 1763 ; 1764 mmio_clrsetbits_32(CTL_REG(i, 93), 0xff << 24, 1765 0x69 << 24); 1766 while (((mmio_read_32(CTL_REG(i, 100)) >> 24) & 0x7f) != 1767 0x40) 1768 ; 1769 } 1770 } 1771 return low_power; 1772 } 1773 1774 void resume_low_power(uint32_t low_power) 1775 { 1776 uint32_t channel_mask; 1777 uint32_t tmp, i, val; 1778 1779 channel_mask = (mmio_read_32(PMUGRF_BASE + PMUGRF_OSREG(2)) >> 28) & 1780 0x3; 1781 for (i = 0; i < 2; i++) { 1782 if (!(channel_mask & (1 << i))) 1783 continue; 1784 1785 /* resume external self-refresh */ 1786 tmp = i ? 12 : 8; 1787 val = (low_power >> (4 + 8 * i)) & 0x1; 1788 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, val << tmp); 1789 /* resume auto low-power */ 1790 val = (low_power >> (8 * i)) & 0x7; 1791 mmio_setbits_32(CTL_REG(i, 101), val); 1792 /* resume stdby mode */ 1793 val = (low_power >> (3 + 8 * i)) & 0x1; 1794 mmio_write_32(CIC_BASE + CIC_CTRL1, 1795 (1 << (i + 16)) | (val << i)); 1796 } 1797 } 1798 1799 static void dram_low_power_config(void) 1800 { 1801 uint32_t tmp, i; 1802 uint32_t ch_cnt = rk3399_dram_status.timing_config.ch_cnt; 1803 uint32_t dram_type = rk3399_dram_status.timing_config.dram_type; 1804 1805 if (dram_type == DDR3) 1806 tmp = (2 << 16) | (0x7 << 8); 1807 else 1808 tmp = (3 << 16) | (0x7 << 8); 1809 1810 for (i = 0; i < ch_cnt; i++) 1811 mmio_clrsetbits_32(CTL_REG(i, 101), 0x70f0f, tmp); 1812 1813 /* standby idle */ 1814 mmio_write_32(CIC_BASE + CIC_CG_WAIT_TH, 0x640008); 1815 1816 if (ch_cnt == 2) { 1817 mmio_write_32(GRF_BASE + GRF_DDRC1_CON1, 1818 (((0x1<<4) | (0x1<<5) | (0x1<<6) | 1819 (0x1<<7)) << 16) | 1820 ((0x1<<4) | (0x0<<5) | (0x1<<6) | (0x1<<7))); 1821 mmio_write_32(CIC_BASE + CIC_CTRL1, 0x002a0028); 1822 } 1823 1824 mmio_write_32(GRF_BASE + GRF_DDRC0_CON1, 1825 (((0x1<<4) | (0x1<<5) | (0x1<<6) | (0x1<<7)) << 16) | 1826 ((0x1<<4) | (0x0<<5) | (0x1<<6) | (0x1<<7))); 1827 mmio_write_32(CIC_BASE + CIC_CTRL1, 0x00150014); 1828 } 1829 1830 void dram_dfs_init(void) 1831 { 1832 uint32_t trefi0, trefi1, boot_freq; 1833 1834 /* get sdram config for os reg */ 1835 get_dram_drv_odt_val(sdram_config.dramtype, 1836 &rk3399_dram_status.drv_odt_lp_cfg); 1837 sdram_timing_cfg_init(&rk3399_dram_status.timing_config, 1838 &sdram_config, 1839 &rk3399_dram_status.drv_odt_lp_cfg); 1840 1841 trefi0 = ((mmio_read_32(CTL_REG(0, 48)) >> 16) & 0xffff) + 8; 1842 trefi1 = ((mmio_read_32(CTL_REG(0, 49)) >> 16) & 0xffff) + 8; 1843 1844 rk3399_dram_status.index_freq[0] = trefi0 * 10 / 39; 1845 rk3399_dram_status.index_freq[1] = trefi1 * 10 / 39; 1846 rk3399_dram_status.current_index = 1847 (mmio_read_32(CTL_REG(0, 111)) >> 16) & 0x3; 1848 if (rk3399_dram_status.timing_config.dram_type == DDR3) { 1849 rk3399_dram_status.index_freq[0] /= 2; 1850 rk3399_dram_status.index_freq[1] /= 2; 1851 } 1852 boot_freq = 1853 rk3399_dram_status.index_freq[rk3399_dram_status.current_index]; 1854 boot_freq = dpll_rates_table[to_get_clk_index(boot_freq)].mhz; 1855 rk3399_dram_status.boot_freq = boot_freq; 1856 rk3399_dram_status.index_freq[rk3399_dram_status.current_index] = 1857 boot_freq; 1858 rk3399_dram_status.index_freq[(rk3399_dram_status.current_index + 1) & 1859 0x1] = 0; 1860 rk3399_dram_status.low_power_stat = 0; 1861 /* 1862 * following register decide if NOC stall the access request 1863 * or return error when NOC being idled. when doing ddr frequency 1864 * scaling in M0 or DCF, we need to make sure noc stall the access 1865 * request, if return error cpu may data abort when ddr frequency 1866 * changing. it don't need to set this register every times, 1867 * so we init this register in function dram_dfs_init(). 1868 */ 1869 mmio_write_32(GRF_BASE + GRF_SOC_CON(0), 0xffffffff); 1870 mmio_write_32(GRF_BASE + GRF_SOC_CON(1), 0xffffffff); 1871 mmio_write_32(GRF_BASE + GRF_SOC_CON(2), 0xffffffff); 1872 mmio_write_32(GRF_BASE + GRF_SOC_CON(3), 0xffffffff); 1873 mmio_write_32(GRF_BASE + GRF_SOC_CON(4), 0x70007000); 1874 1875 /* Disable multicast */ 1876 mmio_clrbits_32(PHY_REG(0, 896), 1); 1877 mmio_clrbits_32(PHY_REG(1, 896), 1); 1878 1879 dram_low_power_config(); 1880 } 1881 1882 /* 1883 * arg0: bit0-7: sr_idle; bit8-15:sr_mc_gate_idle; bit16-31: standby idle 1884 * arg1: bit0-11: pd_idle; bit 16-27: srpd_lite_idle 1885 * arg2: bit0: if odt en 1886 */ 1887 uint32_t dram_set_odt_pd(uint32_t arg0, uint32_t arg1, uint32_t arg2) 1888 { 1889 struct drv_odt_lp_config *lp_cfg = &rk3399_dram_status.drv_odt_lp_cfg; 1890 uint32_t *low_power = &rk3399_dram_status.low_power_stat; 1891 uint32_t dram_type, ch_count, pd_tmp, sr_tmp, i; 1892 1893 dram_type = rk3399_dram_status.timing_config.dram_type; 1894 ch_count = rk3399_dram_status.timing_config.ch_cnt; 1895 1896 lp_cfg->sr_idle = arg0 & 0xff; 1897 lp_cfg->sr_mc_gate_idle = (arg0 >> 8) & 0xff; 1898 lp_cfg->standby_idle = (arg0 >> 16) & 0xffff; 1899 lp_cfg->pd_idle = arg1 & 0xfff; 1900 lp_cfg->srpd_lite_idle = (arg1 >> 16) & 0xfff; 1901 1902 rk3399_dram_status.timing_config.odt = arg2 & 0x1; 1903 1904 exit_low_power(); 1905 1906 *low_power = 0; 1907 1908 /* pd_idle en */ 1909 if (lp_cfg->pd_idle) 1910 *low_power |= ((1 << 0) | (1 << 8)); 1911 /* sr_idle en srpd_lite_idle */ 1912 if (lp_cfg->sr_idle | lp_cfg->srpd_lite_idle) 1913 *low_power |= ((1 << 1) | (1 << 9)); 1914 /* sr_mc_gate_idle */ 1915 if (lp_cfg->sr_mc_gate_idle) 1916 *low_power |= ((1 << 2) | (1 << 10)); 1917 /* standbyidle */ 1918 if (lp_cfg->standby_idle) { 1919 if (rk3399_dram_status.timing_config.ch_cnt == 2) 1920 *low_power |= ((1 << 3) | (1 << 11)); 1921 else 1922 *low_power |= (1 << 3); 1923 } 1924 1925 pd_tmp = arg1; 1926 if (dram_type != LPDDR4) 1927 pd_tmp = arg1 & 0xfff; 1928 sr_tmp = arg0 & 0xffff; 1929 for (i = 0; i < ch_count; i++) { 1930 mmio_write_32(CTL_REG(i, 102), pd_tmp); 1931 mmio_clrsetbits_32(CTL_REG(i, 103), 0xffff, sr_tmp); 1932 } 1933 mmio_write_32(CIC_BASE + CIC_IDLE_TH, (arg0 >> 16) & 0xffff); 1934 1935 return 0; 1936 } 1937 1938 static void m0_configure_ddr(struct pll_div pll_div, uint32_t ddr_index) 1939 { 1940 /* set PARAM to M0_FUNC_DRAM */ 1941 mmio_write_32(M0_PARAM_ADDR + PARAM_M0_FUNC, M0_FUNC_DRAM); 1942 1943 mmio_write_32(M0_PARAM_ADDR + PARAM_DPLL_CON0, FBDIV(pll_div.fbdiv)); 1944 mmio_write_32(M0_PARAM_ADDR + PARAM_DPLL_CON1, 1945 POSTDIV2(pll_div.postdiv2) | POSTDIV1(pll_div.postdiv1) | 1946 REFDIV(pll_div.refdiv)); 1947 1948 mmio_write_32(M0_PARAM_ADDR + PARAM_DRAM_FREQ, pll_div.mhz); 1949 1950 mmio_write_32(M0_PARAM_ADDR + PARAM_FREQ_SELECT, ddr_index << 4); 1951 dmbst(); 1952 } 1953 1954 static uint32_t prepare_ddr_timing(uint32_t mhz) 1955 { 1956 uint32_t index; 1957 struct dram_timing_t dram_timing; 1958 1959 rk3399_dram_status.timing_config.freq = mhz; 1960 1961 if (mhz < 300) 1962 rk3399_dram_status.timing_config.dllbp = 1; 1963 else 1964 rk3399_dram_status.timing_config.dllbp = 0; 1965 1966 if (rk3399_dram_status.timing_config.odt == 1) 1967 gen_rk3399_set_odt(1); 1968 1969 index = (rk3399_dram_status.current_index + 1) & 0x1; 1970 1971 /* 1972 * checking if having available gate traiing timing for 1973 * target freq. 1974 */ 1975 dram_get_parameter(&rk3399_dram_status.timing_config, &dram_timing); 1976 gen_rk3399_ctl_params(&rk3399_dram_status.timing_config, 1977 &dram_timing, index); 1978 gen_rk3399_pi_params(&rk3399_dram_status.timing_config, 1979 &dram_timing, index); 1980 gen_rk3399_phy_params(&rk3399_dram_status.timing_config, 1981 &rk3399_dram_status.drv_odt_lp_cfg, 1982 &dram_timing, index); 1983 rk3399_dram_status.index_freq[index] = mhz; 1984 1985 return index; 1986 } 1987 1988 uint32_t ddr_set_rate(uint32_t hz) 1989 { 1990 uint32_t low_power, index, ddr_index; 1991 uint32_t mhz = hz / (1000 * 1000); 1992 1993 if (mhz == 1994 rk3399_dram_status.index_freq[rk3399_dram_status.current_index]) 1995 return mhz; 1996 1997 index = to_get_clk_index(mhz); 1998 mhz = dpll_rates_table[index].mhz; 1999 2000 ddr_index = prepare_ddr_timing(mhz); 2001 gen_rk3399_enable_training(rk3399_dram_status.timing_config.ch_cnt, 2002 mhz); 2003 if (ddr_index > 1) 2004 goto out; 2005 2006 /* 2007 * Make sure the clock is enabled. The M0 clocks should be on all of the 2008 * time during S0. 2009 */ 2010 m0_configure_ddr(dpll_rates_table[index], ddr_index); 2011 m0_start(); 2012 m0_wait_done(); 2013 m0_stop(); 2014 2015 if (rk3399_dram_status.timing_config.odt == 0) 2016 gen_rk3399_set_odt(0); 2017 2018 rk3399_dram_status.current_index = ddr_index; 2019 low_power = rk3399_dram_status.low_power_stat; 2020 resume_low_power(low_power); 2021 out: 2022 gen_rk3399_disable_training(rk3399_dram_status.timing_config.ch_cnt); 2023 return mhz; 2024 } 2025 2026 uint32_t ddr_round_rate(uint32_t hz) 2027 { 2028 int index; 2029 uint32_t mhz = hz / (1000 * 1000); 2030 2031 index = to_get_clk_index(mhz); 2032 2033 return dpll_rates_table[index].mhz * 1000 * 1000; 2034 } 2035 2036 void ddr_prepare_for_sys_suspend(void) 2037 { 2038 uint32_t mhz = 2039 rk3399_dram_status.index_freq[rk3399_dram_status.current_index]; 2040 2041 /* 2042 * If we're not currently at the boot (assumed highest) frequency, we 2043 * need to change frequencies to configure out current index. 2044 */ 2045 rk3399_suspend_status.freq = mhz; 2046 exit_low_power(); 2047 rk3399_suspend_status.low_power_stat = 2048 rk3399_dram_status.low_power_stat; 2049 rk3399_suspend_status.odt = rk3399_dram_status.timing_config.odt; 2050 rk3399_dram_status.low_power_stat = 0; 2051 rk3399_dram_status.timing_config.odt = 1; 2052 if (mhz != rk3399_dram_status.boot_freq) 2053 ddr_set_rate(rk3399_dram_status.boot_freq * 1000 * 1000); 2054 2055 /* 2056 * This will configure the other index to be the same frequency as the 2057 * current one. We retrain both indices on resume, so both have to be 2058 * setup for the same frequency. 2059 */ 2060 prepare_ddr_timing(rk3399_dram_status.boot_freq); 2061 } 2062 2063 void ddr_prepare_for_sys_resume(void) 2064 { 2065 /* Disable multicast */ 2066 mmio_clrbits_32(PHY_REG(0, 896), 1); 2067 mmio_clrbits_32(PHY_REG(1, 896), 1); 2068 2069 /* The suspend code changes the current index, so reset it now. */ 2070 rk3399_dram_status.current_index = 2071 (mmio_read_32(CTL_REG(0, 111)) >> 16) & 0x3; 2072 rk3399_dram_status.low_power_stat = 2073 rk3399_suspend_status.low_power_stat; 2074 rk3399_dram_status.timing_config.odt = rk3399_suspend_status.odt; 2075 2076 /* 2077 * Set the saved frequency from suspend if it's different than the 2078 * current frequency. 2079 */ 2080 if (rk3399_suspend_status.freq != 2081 rk3399_dram_status.index_freq[rk3399_dram_status.current_index]) { 2082 ddr_set_rate(rk3399_suspend_status.freq * 1000 * 1000); 2083 return; 2084 } 2085 2086 gen_rk3399_set_odt(rk3399_dram_status.timing_config.odt); 2087 resume_low_power(rk3399_dram_status.low_power_stat); 2088 } 2089