1 /* 2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLAT_PRIVATE_H 8 #define PLAT_PRIVATE_H 9 10 #ifndef __ASSEMBLY__ 11 12 #include <stdint.h> 13 14 #include <lib/psci/psci.h> 15 #include <lib/xlat_tables/xlat_tables.h> 16 #include <lib/mmio.h> 17 18 #define __sramdata __attribute__((section(".sram.data"))) 19 #define __sramconst __attribute__((section(".sram.rodata"))) 20 #define __sramfunc __attribute__((section(".sram.text"))) 21 22 #define __pmusramdata __attribute__((section(".pmusram.data"))) 23 #define __pmusramconst __attribute__((section(".pmusram.rodata"))) 24 #define __pmusramfunc __attribute__((section(".pmusram.text"))) 25 26 extern uint32_t __bl31_sram_text_start, __bl31_sram_text_end; 27 extern uint32_t __bl31_sram_data_start, __bl31_sram_data_end; 28 extern uint32_t __bl31_sram_stack_start, __bl31_sram_stack_end; 29 extern uint32_t __bl31_sram_text_real_end, __bl31_sram_data_real_end; 30 extern uint32_t __sram_incbin_start, __sram_incbin_end; 31 extern uint32_t __sram_incbin_real_end; 32 33 struct rockchip_bl31_params { 34 param_header_t h; 35 image_info_t *bl31_image_info; 36 entry_point_info_t *bl32_ep_info; 37 image_info_t *bl32_image_info; 38 entry_point_info_t *bl33_ep_info; 39 image_info_t *bl33_image_info; 40 }; 41 42 /****************************************************************************** 43 * The register have write-mask bits, it is mean, if you want to set the bits, 44 * you needs set the write-mask bits at the same time, 45 * The write-mask bits is in high 16-bits. 46 * The fllowing macro definition helps access write-mask bits reg efficient! 47 ******************************************************************************/ 48 #define REG_MSK_SHIFT 16 49 50 #ifndef WMSK_BIT 51 #define WMSK_BIT(nr) BIT((nr) + REG_MSK_SHIFT) 52 #endif 53 54 /* set one bit with write mask */ 55 #ifndef BIT_WITH_WMSK 56 #define BIT_WITH_WMSK(nr) (BIT(nr) | WMSK_BIT(nr)) 57 #endif 58 59 #ifndef BITS_SHIFT 60 #define BITS_SHIFT(bits, shift) (bits << (shift)) 61 #endif 62 63 #ifndef BITS_WITH_WMASK 64 #define BITS_WITH_WMASK(bits, msk, shift)\ 65 (BITS_SHIFT(bits, shift) | BITS_SHIFT(msk, (shift + REG_MSK_SHIFT))) 66 #endif 67 68 /****************************************************************************** 69 * Function and variable prototypes 70 *****************************************************************************/ 71 void plat_configure_mmu_el3(unsigned long total_base, 72 unsigned long total_size, 73 unsigned long, 74 unsigned long, 75 unsigned long, 76 unsigned long); 77 78 void plat_cci_init(void); 79 void plat_cci_enable(void); 80 void plat_cci_disable(void); 81 82 void plat_delay_timer_init(void); 83 84 void params_early_setup(void *plat_params_from_bl2); 85 86 void plat_rockchip_gic_driver_init(void); 87 void plat_rockchip_gic_init(void); 88 void plat_rockchip_gic_cpuif_enable(void); 89 void plat_rockchip_gic_cpuif_disable(void); 90 void plat_rockchip_gic_pcpu_init(void); 91 92 void plat_rockchip_pmu_init(void); 93 void plat_rockchip_soc_init(void); 94 uintptr_t plat_get_sec_entrypoint(void); 95 96 void platform_cpu_warmboot(void); 97 98 struct gpio_info *plat_get_rockchip_gpio_reset(void); 99 struct gpio_info *plat_get_rockchip_gpio_poweroff(void); 100 struct gpio_info *plat_get_rockchip_suspend_gpio(uint32_t *count); 101 struct apio_info *plat_get_rockchip_suspend_apio(void); 102 void plat_rockchip_gpio_init(void); 103 void plat_rockchip_save_gpio(void); 104 void plat_rockchip_restore_gpio(void); 105 106 int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint); 107 int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl, 108 plat_local_state_t lvl_state); 109 int rockchip_soc_cores_pwr_dm_off(void); 110 int rockchip_soc_sys_pwr_dm_suspend(void); 111 int rockchip_soc_cores_pwr_dm_suspend(void); 112 int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl, 113 plat_local_state_t lvl_state); 114 int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl, 115 plat_local_state_t lvl_state); 116 int rockchip_soc_cores_pwr_dm_on_finish(void); 117 int rockchip_soc_sys_pwr_dm_resume(void); 118 119 int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl, 120 plat_local_state_t lvl_state); 121 int rockchip_soc_cores_pwr_dm_resume(void); 122 void __dead2 rockchip_soc_soft_reset(void); 123 void __dead2 rockchip_soc_system_off(void); 124 void __dead2 rockchip_soc_cores_pd_pwr_dn_wfi( 125 const psci_power_state_t *target_state); 126 void __dead2 rockchip_soc_sys_pd_pwr_dn_wfi(void); 127 128 extern const unsigned char rockchip_power_domain_tree_desc[]; 129 130 extern void *pmu_cpuson_entrypoint; 131 extern uint64_t cpuson_entry_point[PLATFORM_CORE_COUNT]; 132 extern uint32_t cpuson_flags[PLATFORM_CORE_COUNT]; 133 134 extern const mmap_region_t plat_rk_mmap[]; 135 136 void rockchip_plat_mmu_el3(void); 137 138 #endif /* __ASSEMBLY__ */ 139 140 /****************************************************************************** 141 * cpu up status 142 * The bits of macro value is not more than 12 bits for cmp instruction! 143 ******************************************************************************/ 144 #define PMU_CPU_HOTPLUG 0xf00 145 #define PMU_CPU_AUTO_PWRDN 0xf0 146 #define PMU_CLST_RET 0xa5 147 148 #endif /* PLAT_PRIVATE_H */ 149