1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __EP_INFO_H__ 8 #define __EP_INFO_H__ 9 10 #include <param_header.h> 11 12 #define SECURE 0x0 13 #define NON_SECURE 0x1 14 #define sec_state_is_valid(s) (((s) == SECURE) || ((s) == NON_SECURE)) 15 16 /******************************************************************************* 17 * Constants that allow assembler code to access members of and the 18 * 'entry_point_info' structure at their correct offsets. 19 ******************************************************************************/ 20 #define ENTRY_POINT_INFO_PC_OFFSET 0x08 21 #ifdef AARCH32 22 #define ENTRY_POINT_INFO_ARGS_OFFSET 0x10 23 #else 24 #define ENTRY_POINT_INFO_ARGS_OFFSET 0x18 25 #endif 26 27 /* The following are used to set/get image attributes. */ 28 #define PARAM_EP_SECURITY_MASK (0x1) 29 30 #define GET_SECURITY_STATE(x) (x & PARAM_EP_SECURITY_MASK) 31 #define SET_SECURITY_STATE(x, security) \ 32 ((x) = ((x) & ~PARAM_EP_SECURITY_MASK) | (security)) 33 34 #define EP_EE_MASK 0x2 35 #define EP_EE_LITTLE 0x0 36 #define EP_EE_BIG 0x2 37 #define EP_GET_EE(x) (x & EP_EE_MASK) 38 #define EP_SET_EE(x, ee) ((x) = ((x) & ~EP_EE_MASK) | (ee)) 39 40 #define EP_ST_MASK 0x4 41 #define EP_ST_DISABLE 0x0 42 #define EP_ST_ENABLE 0x4 43 #define EP_GET_ST(x) (x & EP_ST_MASK) 44 #define EP_SET_ST(x, ee) ((x) = ((x) & ~EP_ST_MASK) | (ee)) 45 46 #define EP_EXE_MASK 0x8 47 #define NON_EXECUTABLE 0x0 48 #define EXECUTABLE 0x8 49 #define EP_GET_EXE(x) (x & EP_EXE_MASK) 50 #define EP_SET_EXE(x, ee) ((x) = ((x) & ~EP_EXE_MASK) | (ee)) 51 52 #define EP_FIRST_EXE_MASK 0x10 53 #define EP_FIRST_EXE 0x10 54 #define EP_GET_FIRST_EXE(x) ((x) & EP_FIRST_EXE_MASK) 55 #define EP_SET_FIRST_EXE(x, ee) ((x) = ((x) & ~EP_FIRST_EXE_MASK) | (ee)) 56 57 #ifndef __ASSEMBLY__ 58 59 #include <cassert.h> 60 #include <types.h> 61 62 typedef struct aapcs64_params { 63 u_register_t arg0; 64 u_register_t arg1; 65 u_register_t arg2; 66 u_register_t arg3; 67 u_register_t arg4; 68 u_register_t arg5; 69 u_register_t arg6; 70 u_register_t arg7; 71 } aapcs64_params_t; 72 73 typedef struct aapcs32_params { 74 u_register_t arg0; 75 u_register_t arg1; 76 u_register_t arg2; 77 u_register_t arg3; 78 } aapcs32_params_t; 79 80 /***************************************************************************** 81 * This structure represents the superset of information needed while 82 * switching exception levels. The only two mechanisms to do so are 83 * ERET & SMC. Security state is indicated using bit zero of header 84 * attribute 85 * NOTE: BL1 expects entrypoint followed by spsr at an offset from the start 86 * of this structure defined by the macro `ENTRY_POINT_INFO_PC_OFFSET` while 87 * processing SMC to jump to BL31. 88 *****************************************************************************/ 89 typedef struct entry_point_info { 90 param_header_t h; 91 uintptr_t pc; 92 uint32_t spsr; 93 #ifdef AARCH32 94 aapcs32_params_t args; 95 #else 96 aapcs64_params_t args; 97 #endif 98 } entry_point_info_t; 99 100 /* 101 * Compile time assertions related to the 'entry_point_info' structure to 102 * ensure that the assembler and the compiler view of the offsets of 103 * the structure members is the same. 104 */ 105 CASSERT(ENTRY_POINT_INFO_PC_OFFSET == 106 __builtin_offsetof(entry_point_info_t, pc), \ 107 assert_BL31_pc_offset_mismatch); 108 109 CASSERT(ENTRY_POINT_INFO_ARGS_OFFSET == \ 110 __builtin_offsetof(entry_point_info_t, args), \ 111 assert_BL31_args_offset_mismatch); 112 113 CASSERT(sizeof(uintptr_t) == 114 __builtin_offsetof(entry_point_info_t, spsr) - \ 115 __builtin_offsetof(entry_point_info_t, pc), \ 116 assert_entrypoint_and_spsr_should_be_adjacent); 117 118 #endif /*__ASSEMBLY__*/ 119 120 #endif /* __EP_INFO_H__ */ 121 122