1# 2# Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Default, static values for build variables, listed in alphabetic order. 8# Dependencies between build options, if any, are handled in the top-level 9# Makefile, after this file is included. This ensures that the former is better 10# poised to handle dependencies, as all build variables would have a default 11# value by then. 12 13# Use T32 by default 14AARCH32_INSTRUCTION_SET := T32 15 16# The AArch32 Secure Payload to be built as BL32 image 17AARCH32_SP := none 18 19# The Target build architecture. Supported values are: aarch64, aarch32. 20ARCH := aarch64 21 22# ARM Architecture major and minor versions: 8.0 by default. 23ARM_ARCH_MAJOR := 8 24ARM_ARCH_MINOR := 0 25 26# Base commit to perform code check on 27BASE_COMMIT := origin/master 28 29# Execute BL2 at EL3 30BL2_AT_EL3 := 0 31 32# BL2 image is stored in XIP memory, for now, this option is only supported 33# when BL2_AT_EL3 is 1. 34BL2_IN_XIP_MEM := 0 35 36# By default, consider that the platform may release several CPUs out of reset. 37# The platform Makefile is free to override this value. 38COLD_BOOT_SINGLE_CPU := 0 39 40# Flag to compile in coreboot support code. Exclude by default. The coreboot 41# Makefile system will set this when compiling TF as part of a coreboot image. 42COREBOOT := 0 43 44# For Chain of Trust 45CREATE_KEYS := 1 46 47# Build flag to include AArch32 registers in cpu context save and restore during 48# world switch. This flag must be set to 0 for AArch64-only platforms. 49CTX_INCLUDE_AARCH32_REGS := 1 50 51# Include FP registers in cpu context 52CTX_INCLUDE_FPREGS := 0 53 54# Debug build 55DEBUG := 0 56 57# Build platform 58DEFAULT_PLAT := fvp 59 60# Enable capability to disable authentication dynamically. Only meant for 61# development platforms. 62DYN_DISABLE_AUTH := 0 63 64# Build option to enable MPAM for lower ELs 65ENABLE_MPAM_FOR_LOWER_ELS := 0 66 67# Flag to Enable Position Independant support (PIE) 68ENABLE_PIE := 0 69 70# Flag to enable Performance Measurement Framework 71ENABLE_PMF := 0 72 73# Flag to enable PSCI STATs functionality 74ENABLE_PSCI_STAT := 0 75 76# Flag to enable runtime instrumentation using PMF 77ENABLE_RUNTIME_INSTRUMENTATION := 0 78 79# Flag to enable stack corruption protection 80ENABLE_STACK_PROTECTOR := 0 81 82# Flag to enable exception handling in EL3 83EL3_EXCEPTION_HANDLING := 0 84 85# Build flag to treat usage of deprecated platform and framework APIs as error. 86ERROR_DEPRECATED := 0 87 88# Fault injection support 89FAULT_INJECTION_SUPPORT := 0 90 91# Byte alignment that each component in FIP is aligned to 92FIP_ALIGN := 0 93 94# Default FIP file name 95FIP_NAME := fip.bin 96 97# Default FWU_FIP file name 98FWU_FIP_NAME := fwu_fip.bin 99 100# For Chain of Trust 101GENERATE_COT := 0 102 103# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By 104# default, they are for Secure EL1. 105GICV2_G0_FOR_EL3 := 0 106 107# Route External Aborts to EL3. Disabled by default; External Aborts are handled 108# by lower ELs. 109HANDLE_EA_EL3_FIRST := 0 110 111# Whether system coherency is managed in hardware, without explicit software 112# operations. 113HW_ASSISTED_COHERENCY := 0 114 115# Set the default algorithm for the generation of Trusted Board Boot keys 116KEY_ALG := rsa 117 118# Enable use of the console API allowing multiple consoles to be registered 119# at the same time. 120MULTI_CONSOLE_API := 0 121 122# NS timer register save and restore 123NS_TIMER_SWITCH := 0 124 125# Build PL011 UART driver in minimal generic UART mode 126PL011_GENERIC_UART := 0 127 128# By default, consider that the platform's reset address is not programmable. 129# The platform Makefile is free to override this value. 130PROGRAMMABLE_RESET_ADDRESS := 0 131 132# Flag used to choose the power state format viz Extended State-ID or the 133# Original format. 134PSCI_EXTENDED_STATE_ID := 0 135 136# Enable RAS support 137RAS_EXTENSION := 0 138 139# By default, BL1 acts as the reset handler, not BL31 140RESET_TO_BL31 := 0 141 142# For Chain of Trust 143SAVE_KEYS := 0 144 145# Software Delegated Exception support 146SDEI_SUPPORT := 0 147 148# Whether code and read-only data should be put on separate memory pages. The 149# platform Makefile is free to override this value. 150SEPARATE_CODE_AND_RODATA := 0 151 152# If the BL31 image initialisation code is recalimed after use for the secondary 153# cores stack 154RECLAIM_INIT_CODE := 0 155 156# Default to SMCCC Version 1.X 157SMCCC_MAJOR_VERSION := 1 158 159# SPD choice 160SPD := none 161 162# For including the Secure Partition Manager 163ENABLE_SPM := 0 164 165# Flag to introduce an infinite loop in BL1 just before it exits into the next 166# image. This is meant to help debugging the post-BL2 phase. 167SPIN_ON_BL1_EXIT := 0 168 169# Flags to build TF with Trusted Boot support 170TRUSTED_BOARD_BOOT := 0 171 172# Build option to choose whether Trusted Firmware uses Coherent memory or not. 173USE_COHERENT_MEM := 1 174 175# Build option to choose whether Trusted Firmware uses library at ROM 176USE_ROMLIB := 0 177 178# Use tbbr_oid.h instead of platform_oid.h 179USE_TBBR_DEFS := 1 180 181# Build verbosity 182V := 0 183 184# Whether to enable D-Cache early during warm boot. This is usually 185# applicable for platforms wherein interconnect programming is not 186# required to enable cache coherency after warm reset (eg: single cluster 187# platforms). 188WARMBOOT_ENABLE_DCACHE_EARLY := 0 189 190# Build option to enable/disable the Statistical Profiling Extensions 191ENABLE_SPE_FOR_LOWER_ELS := 1 192 193# SPE is only supported on AArch64 so disable it on AArch32. 194ifeq (${ARCH},aarch32) 195 override ENABLE_SPE_FOR_LOWER_ELS := 0 196endif 197 198ENABLE_AMU := 0 199 200# By default, enable Scalable Vector Extension if implemented for Non-secure 201# lower ELs 202# Note SVE is only supported on AArch64 - therefore do not enable in AArch32 203ifneq (${ARCH},aarch32) 204 ENABLE_SVE_FOR_NS := 1 205else 206 override ENABLE_SVE_FOR_NS := 0 207endif 208