1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5 */ 6 7/dts-v1/; 8 9#include "stm32mp157c.dtsi" 10#include "stm32mp157caa-pinctrl.dtsi" 11 12/ { 13 model = "STMicroelectronics STM32MP157C-ED1 pmic eval daughter"; 14 compatible = "st,stm32mp157c-ed1", "st,stm32mp157"; 15 16 chosen { 17 bootargs = "earlyprintk console=ttyS3,115200 root=/dev/ram"; 18 stdout-path = "serial3:115200n8"; 19 }; 20}; 21 22&i2c4 { 23 pinctrl-names = "default"; 24 pinctrl-0 = <&i2c4_pins_a>; 25 i2c-scl-rising-time-ns = <185>; 26 i2c-scl-falling-time-ns = <20>; 27 status = "okay"; 28 29 pmic: stpmu1@33 { 30 compatible = "st,stpmu1"; 31 reg = <0x33>; 32 status = "okay"; 33 34 st,main_control_register = <0x04>; 35 st,vin_control_register = <0xc0>; 36 st,usb_control_register = <0x30>; 37 38 regulators { 39 compatible = "st,stpmu1-regulators"; 40 41 v3v3: buck4 { 42 regulator-name = "v3v3"; 43 regulator-min-microvolt = <3300000>; 44 regulator-max-microvolt = <3300000>; 45 regulator-boot-on; 46 regulator-over-current-protection; 47 regulator-initial-mode = <8>; 48 49 regulator-state-standby { 50 regulator-suspend-microvolt = <3300000>; 51 regulator-unchanged-in-suspend; 52 regulator-mode = <8>; 53 }; 54 regulator-state-mem { 55 regulator-off-in-suspend; 56 }; 57 regulator-state-disk { 58 regulator-off-in-suspend; 59 }; 60 }; 61 62 vdd_sd: ldo5 { 63 regulator-name = "vdd_sd"; 64 regulator-min-microvolt = <2900000>; 65 regulator-max-microvolt = <2900000>; 66 regulator-boot-on; 67 68 regulator-state-standby { 69 regulator-suspend-microvolt = <2900000>; 70 regulator-unchanged-in-suspend; 71 }; 72 regulator-state-mem { 73 regulator-off-in-suspend; 74 }; 75 regulator-state-disk { 76 regulator-off-in-suspend; 77 }; 78 }; 79 }; 80 }; 81}; 82 83&iwdg2 { 84 instance = <2>; 85 timeout-sec = <32>; 86 status = "okay"; 87}; 88 89&rng1 { 90 status = "okay"; 91}; 92 93&sdmmc1 { 94 pinctrl-names = "default"; 95 pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; 96 broken-cd; 97 st,dirpol; 98 st,negedge; 99 st,pin-ckin; 100 bus-width = <4>; 101 sd-uhs-sdr12; 102 sd-uhs-sdr25; 103 sd-uhs-sdr50; 104 sd-uhs-ddr50; 105 sd-uhs-sdr104; 106 status = "okay"; 107}; 108 109&sdmmc2 { 110 pinctrl-names = "default"; 111 pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; 112 non-removable; 113 no-sd; 114 no-sdio; 115 st,dirpol; 116 st,negedge; 117 bus-width = <8>; 118 status = "okay"; 119}; 120 121&uart4 { 122 pinctrl-names = "default"; 123 pinctrl-0 = <&uart4_pins_a>; 124 resets = <&rcc UART4_R>; 125 status = "okay"; 126}; 127 128/* ATF Specific */ 129#include <dt-bindings/clock/stm32mp1-clksrc.h> 130#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi" 131 132/ { 133 aliases { 134 gpio0 = &gpioa; 135 gpio1 = &gpiob; 136 gpio2 = &gpioc; 137 gpio3 = &gpiod; 138 gpio4 = &gpioe; 139 gpio5 = &gpiof; 140 gpio6 = &gpiog; 141 gpio7 = &gpioh; 142 gpio8 = &gpioi; 143 gpio9 = &gpioj; 144 gpio10 = &gpiok; 145 gpio25 = &gpioz; 146 i2c3 = &i2c4; 147 }; 148 149 soc { 150 stgen: stgen@5C008000 { 151 compatible = "st,stm32-stgen"; 152 reg = <0x5C008000 0x1000>; 153 status = "okay"; 154 }; 155 }; 156}; 157 158/* CLOCK init */ 159&rcc { 160 st,clksrc = < 161 CLK_MPU_PLL1P 162 CLK_AXI_PLL2P 163 CLK_PLL12_HSE 164 CLK_PLL3_HSE 165 CLK_PLL4_HSE 166 CLK_RTC_LSE 167 CLK_MCO1_DISABLED 168 CLK_MCO2_DISABLED 169 >; 170 171 st,clkdiv = < 172 1 /*MPU*/ 173 0 /*AXI*/ 174 1 /*APB1*/ 175 1 /*APB2*/ 176 1 /*APB3*/ 177 1 /*APB4*/ 178 2 /*APB5*/ 179 23 /*RTC*/ 180 0 /*MCO1*/ 181 0 /*MCO2*/ 182 >; 183 184 st,pkcs = < 185 CLK_CKPER_HSE 186 CLK_FMC_ACLK 187 CLK_QSPI_ACLK 188 CLK_ETH_DISABLED 189 CLK_SDMMC12_PLL3R 190 CLK_DSI_DSIPLL 191 CLK_STGEN_HSE 192 CLK_USBPHY_HSE 193 CLK_SPI2S1_PLL3Q 194 CLK_SPI2S23_PLL3Q 195 CLK_SPI45_HSI 196 CLK_SPI6_HSI 197 CLK_I2C46_HSI 198 CLK_SDMMC3_PLL3R 199 CLK_USBO_USBPHY 200 CLK_ADC_CKPER 201 CLK_CEC_LSE 202 CLK_I2C12_HSI 203 CLK_I2C35_HSI 204 CLK_UART1_HSI 205 CLK_UART24_HSI 206 CLK_UART35_HSI 207 CLK_UART6_HSI 208 CLK_UART78_HSI 209 CLK_SPDIF_PLL3Q 210 CLK_FDCAN_PLL4Q 211 CLK_SAI1_PLL3Q 212 CLK_SAI2_PLL3Q 213 CLK_SAI3_PLL3Q 214 CLK_SAI4_PLL3Q 215 CLK_RNG1_CSI 216 CLK_RNG2_CSI 217 CLK_LPTIM1_PCLK1 218 CLK_LPTIM23_PCLK3 219 CLK_LPTIM45_PCLK3 220 >; 221 222 /* VCO = 1300.0 MHz => P = 650 (CPU) */ 223 pll1: st,pll@0 { 224 cfg = < 2 80 0 0 0 PQR(1,0,0) >; 225 frac = < 0x800 >; 226 }; 227 228 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ 229 pll2: st,pll@1 { 230 cfg = < 2 65 1 0 0 PQR(1,1,1) >; 231 frac = < 0x1400 >; 232 }; 233 234 /* VCO = 786.4 MHz => P = 197, Q = 49, R = 98 */ 235 pll3: st,pll@2 { 236 cfg = < 2 97 3 15 7 PQR(1,1,1) >; 237 frac = < 0x9ba >; 238 }; 239 240 /* VCO = 508.0 MHz => P = 56, Q = 56, R = 56 */ 241 pll4: st,pll@3 { 242 cfg = < 5 126 8 8 8 PQR(1,1,1) >; 243 }; 244}; 245 246/delete-node/ &clk_csi; 247