1 /* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <assert.h> 7 #include <bl_common.h> 8 #include <common_def.h> 9 #include <console.h> 10 #include <debug.h> 11 #include <generic_delay_timer.h> 12 #include <mcucfg.h> 13 #include <mmio.h> 14 #include <mtcmos.h> 15 #include <mtk_plat_common.h> 16 #include <plat_arm.h> 17 #include <plat_private.h> 18 #include <platform.h> 19 #include <spm.h> 20 21 static entry_point_info_t bl32_ep_info; 22 static entry_point_info_t bl33_ep_info; 23 24 static void platform_setup_cpu(void) 25 { 26 /* turn off all the little core's power except cpu 0 */ 27 mtcmos_little_cpu_off(); 28 29 /* setup big cores */ 30 mmio_write_32((uintptr_t)&mt8173_mcucfg->mp1_config_res, 31 MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK | 32 MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK | 33 MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK | 34 MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK | 35 MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK); 36 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, MP1_AINACTS); 37 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_clkenm_div, 38 MP1_SW_CG_GEN); 39 mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp1_rst_ctl, 40 MP1_L2RSTDISABLE); 41 42 /* set big cores arm64 boot mode */ 43 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_cpucfg, 44 MP1_CPUCFG_64BIT); 45 46 /* set LITTLE cores arm64 boot mode */ 47 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp0_rv_addr[0].rv_addr_hw, 48 MP0_CPUCFG_64BIT); 49 50 /* enable dcm control */ 51 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->bus_fabric_dcm_ctrl, 52 ADB400_GRP_DCM_EN | CCI400_GRP_DCM_EN | ADBCLK_GRP_DCM_EN | 53 EMICLK_GRP_DCM_EN | ACLK_GRP_DCM_EN | L2C_IDLE_DCM_EN | 54 INFRACLK_PSYS_DYNAMIC_CG_EN); 55 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->l2c_sram_ctrl, 56 L2C_SRAM_DCM_EN); 57 mmio_setbits_32((uintptr_t)&mt8173_mcucfg->cci_clk_ctrl, 58 MCU_BUS_DCM_EN); 59 } 60 61 static void platform_setup_sram(void) 62 { 63 /* protect BL31 memory from non-secure read/write access */ 64 mmio_write_32(SRAMROM_SEC_ADDR, (uint32_t)(BL31_END + 0x3ff) & 0x3fc00); 65 mmio_write_32(SRAMROM_SEC_CTRL, 0x10000ff9); 66 } 67 68 /******************************************************************************* 69 * Return a pointer to the 'entry_point_info' structure of the next image for 70 * the security state specified. BL33 corresponds to the non-secure image type 71 * while BL32 corresponds to the secure image type. A NULL pointer is returned 72 * if the image does not exist. 73 ******************************************************************************/ 74 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 75 { 76 entry_point_info_t *next_image_info; 77 78 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 79 80 /* None of the images on this platform can have 0x0 as the entrypoint */ 81 if (next_image_info->pc) 82 return next_image_info; 83 else 84 return NULL; 85 } 86 87 /******************************************************************************* 88 * Perform any BL3-1 early platform setup. Here is an opportunity to copy 89 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before they 90 * are lost (potentially). This needs to be done before the MMU is initialized 91 * so that the memory layout can be used while creating page tables. 92 * BL2 has flushed this information to memory, so we are guaranteed to pick up 93 * good data. 94 ******************************************************************************/ 95 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 96 u_register_t arg2, u_register_t arg3) 97 { 98 struct mtk_bl31_params *arg_from_bl2 = (struct mtk_bl31_params *)arg0; 99 100 console_init(MT8173_UART0_BASE, MT8173_UART_CLOCK, MT8173_BAUDRATE); 101 102 VERBOSE("bl31_setup\n"); 103 104 assert(arg_from_bl2 != NULL); 105 assert(arg_from_bl2->h.type == PARAM_BL31); 106 assert(arg_from_bl2->h.version >= VERSION_1); 107 108 bl32_ep_info = *arg_from_bl2->bl32_ep_info; 109 bl33_ep_info = *arg_from_bl2->bl33_ep_info; 110 } 111 112 /******************************************************************************* 113 * Perform any BL3-1 platform setup code 114 ******************************************************************************/ 115 void bl31_platform_setup(void) 116 { 117 platform_setup_cpu(); 118 platform_setup_sram(); 119 120 generic_delay_timer_init(); 121 122 /* Initialize the gic cpu and distributor interfaces */ 123 plat_arm_gic_driver_init(); 124 plat_arm_gic_init(); 125 126 /* Initialize spm at boot time */ 127 spm_boot_init(); 128 } 129 130 /******************************************************************************* 131 * Perform the very early platform specific architectural setup here. At the 132 * moment this is only intializes the mmu in a quick and dirty way. 133 ******************************************************************************/ 134 void bl31_plat_arch_setup(void) 135 { 136 plat_cci_init(); 137 plat_cci_enable(); 138 139 plat_configure_mmu_el3(BL_CODE_BASE, 140 BL_COHERENT_RAM_END - BL_CODE_BASE, 141 BL_CODE_BASE, 142 BL_CODE_END, 143 BL_COHERENT_RAM_BASE, 144 BL_COHERENT_RAM_END); 145 } 146 147