1 /* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <arch_helpers.h> 7 #include <bl_common.h> 8 #include <cci.h> 9 #include <debug.h> 10 #include <mt8173_def.h> 11 #include <platform_def.h> 12 #include <utils.h> 13 #include <xlat_tables.h> 14 15 static const int cci_map[] = { 16 PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX, 17 PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX 18 }; 19 20 /* Table of regions to map using the MMU. */ 21 const mmap_region_t plat_mmap[] = { 22 /* for TF text, RO, RW */ 23 MAP_REGION_FLAT(TZRAM_BASE, TZRAM_SIZE, 24 MT_MEMORY | MT_RW | MT_SECURE), 25 MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE, 26 MT_DEVICE | MT_RW | MT_SECURE), 27 MAP_REGION_FLAT(MTK_DEV_RNG1_BASE, MTK_DEV_RNG1_SIZE, 28 MT_DEVICE | MT_RW | MT_SECURE), 29 { 0 } 30 31 }; 32 33 /******************************************************************************* 34 * Macro generating the code for the function setting up the pagetables as per 35 * the platform memory map & initialize the mmu, for the given exception level 36 ******************************************************************************/ 37 #define DEFINE_CONFIGURE_MMU_EL(_el) \ 38 void plat_configure_mmu_el ## _el(unsigned long total_base, \ 39 unsigned long total_size, \ 40 unsigned long ro_start, \ 41 unsigned long ro_limit, \ 42 unsigned long coh_start, \ 43 unsigned long coh_limit) \ 44 { \ 45 mmap_add_region(total_base, total_base, \ 46 total_size, \ 47 MT_MEMORY | MT_RW | MT_SECURE); \ 48 mmap_add_region(ro_start, ro_start, \ 49 ro_limit - ro_start, \ 50 MT_MEMORY | MT_RO | MT_SECURE); \ 51 mmap_add_region(coh_start, coh_start, \ 52 coh_limit - coh_start, \ 53 MT_DEVICE | MT_RW | MT_SECURE); \ 54 mmap_add(plat_mmap); \ 55 init_xlat_tables(); \ 56 \ 57 enable_mmu_el ## _el(0); \ 58 } 59 60 /* Define EL3 variants of the function initialising the MMU */ 61 DEFINE_CONFIGURE_MMU_EL(3) 62 63 unsigned int plat_get_syscnt_freq2(void) 64 { 65 return SYS_COUNTER_FREQ_IN_TICKS; 66 } 67 68 void plat_cci_init(void) 69 { 70 /* Initialize CCI driver */ 71 cci_init(PLAT_MT_CCI_BASE, cci_map, ARRAY_SIZE(cci_map)); 72 } 73 74 void plat_cci_enable(void) 75 { 76 /* 77 * Enable CCI coherency for this cluster. 78 * No need for locks as no other cpu is active at the moment. 79 */ 80 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); 81 } 82 83 void plat_cci_disable(void) 84 { 85 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); 86 } 87