1 /* 2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 #include <arch.h> 11 #include "../zynqmp_def.h" 12 13 /******************************************************************************* 14 * Generic platform constants 15 ******************************************************************************/ 16 17 /* Size of cacheable stacks */ 18 #define PLATFORM_STACK_SIZE 0x440 19 20 #define PLATFORM_CORE_COUNT 4 21 #define PLAT_NUM_POWER_DOMAINS 5 22 #define PLAT_MAX_PWR_LVL 1 23 #define PLAT_MAX_RET_STATE 1 24 #define PLAT_MAX_OFF_STATE 2 25 26 /******************************************************************************* 27 * BL31 specific defines. 28 ******************************************************************************/ 29 /* 30 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if 31 * present). BL31_BASE is calculated using the current BL31 debug size plus a 32 * little space for growth. 33 */ 34 #ifndef ZYNQMP_ATF_MEM_BASE 35 # define BL31_BASE 0xfffea000 36 # define BL31_LIMIT 0xffffffff 37 #else 38 # define BL31_BASE (ZYNQMP_ATF_MEM_BASE) 39 # define BL31_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_SIZE - 1) 40 # ifdef ZYNQMP_ATF_MEM_PROGBITS_SIZE 41 # define BL31_PROGBITS_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_PROGBITS_SIZE - 1) 42 # endif 43 #endif 44 45 /******************************************************************************* 46 * BL32 specific defines. 47 ******************************************************************************/ 48 #ifndef ZYNQMP_BL32_MEM_BASE 49 # define BL32_BASE 0x60000000 50 # define BL32_LIMIT 0x7fffffff 51 #else 52 # define BL32_BASE (ZYNQMP_BL32_MEM_BASE) 53 # define BL32_LIMIT (ZYNQMP_BL32_MEM_BASE + ZYNQMP_BL32_MEM_SIZE - 1) 54 #endif 55 56 /******************************************************************************* 57 * BL33 specific defines. 58 ******************************************************************************/ 59 #ifndef PRELOADED_BL33_BASE 60 # define PLAT_ARM_NS_IMAGE_OFFSET 0x8000000 61 #else 62 # define PLAT_ARM_NS_IMAGE_OFFSET PRELOADED_BL33_BASE 63 #endif 64 65 /******************************************************************************* 66 * TSP specific defines. 67 ******************************************************************************/ 68 #define TSP_SEC_MEM_BASE BL32_BASE 69 #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) 70 71 /* ID of the secure physical generic timer interrupt used by the TSP */ 72 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 73 74 /******************************************************************************* 75 * Platform specific page table and MMU setup constants 76 ******************************************************************************/ 77 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) 78 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) 79 #define MAX_MMAP_REGIONS 7 80 #define MAX_XLAT_TABLES 5 81 82 #define CACHE_WRITEBACK_SHIFT 6 83 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 84 85 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 86 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 87 /* 88 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 89 * terminology. On a GICv2 system or mode, the lists will be merged and treated 90 * as Group 0 interrupts. 91 */ 92 #define PLAT_ARM_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER, \ 93 ARM_IRQ_SEC_SGI_0, \ 94 ARM_IRQ_SEC_SGI_1, \ 95 ARM_IRQ_SEC_SGI_2, \ 96 ARM_IRQ_SEC_SGI_3, \ 97 ARM_IRQ_SEC_SGI_4, \ 98 ARM_IRQ_SEC_SGI_5, \ 99 ARM_IRQ_SEC_SGI_6, \ 100 ARM_IRQ_SEC_SGI_7 101 102 #define PLAT_ARM_G0_IRQS 103 104 #endif /* __PLATFORM_DEF_H__ */ 105