1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <common/desc_image_load.h> 16 #include <drivers/generic_delay_timer.h> 17 #ifdef SPD_opteed 18 #include <lib/optee_utils.h> 19 #endif 20 #include <lib/utils.h> 21 #include <plat/common/platform.h> 22 23 #include <arm_def.h> 24 #include <plat_arm.h> 25 26 /* Data structure which holds the extents of the trusted SRAM for BL2 */ 27 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 28 29 /* 30 * Check that BL2_BASE is above ARM_TB_FW_CONFIG_LIMIT. This reserved page is 31 * for `meminfo_t` data structure and fw_configs passed from BL1. 32 */ 33 CASSERT(BL2_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl2_base_overflows); 34 35 /* Weak definitions may be overridden in specific ARM standard platform */ 36 #pragma weak bl2_early_platform_setup2 37 #pragma weak bl2_platform_setup 38 #pragma weak bl2_plat_arch_setup 39 #pragma weak bl2_plat_sec_mem_layout 40 41 #define MAP_BL2_TOTAL MAP_REGION_FLAT( \ 42 bl2_tzram_layout.total_base, \ 43 bl2_tzram_layout.total_size, \ 44 MT_MEMORY | MT_RW | MT_SECURE) 45 46 47 #pragma weak arm_bl2_plat_handle_post_image_load 48 49 /******************************************************************************* 50 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 51 * in x0. This memory layout is sitting at the base of the free trusted SRAM. 52 * Copy it to a safe location before its reclaimed by later BL2 functionality. 53 ******************************************************************************/ 54 void arm_bl2_early_platform_setup(uintptr_t tb_fw_config, 55 struct meminfo *mem_layout) 56 { 57 /* Initialize the console to provide early debug support */ 58 arm_console_boot_init(); 59 60 /* Setup the BL2 memory layout */ 61 bl2_tzram_layout = *mem_layout; 62 63 /* Initialise the IO layer and register platform IO devices */ 64 plat_arm_io_setup(); 65 66 if (tb_fw_config != 0U) 67 arm_bl2_set_tb_cfg_addr((void *)tb_fw_config); 68 } 69 70 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) 71 { 72 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); 73 74 generic_delay_timer_init(); 75 } 76 77 /* 78 * Perform BL2 preload setup. Currently we initialise the dynamic 79 * configuration here. 80 */ 81 void bl2_plat_preload_setup(void) 82 { 83 arm_bl2_dyn_cfg_init(); 84 } 85 86 /* 87 * Perform ARM standard platform setup. 88 */ 89 void arm_bl2_platform_setup(void) 90 { 91 /* Initialize the secure environment */ 92 plat_arm_security_setup(); 93 94 #if defined(PLAT_ARM_MEM_PROT_ADDR) 95 arm_nor_psci_do_static_mem_protect(); 96 #endif 97 } 98 99 void bl2_platform_setup(void) 100 { 101 arm_bl2_platform_setup(); 102 } 103 104 /******************************************************************************* 105 * Perform the very early platform specific architectural setup here. At the 106 * moment this is only initializes the mmu in a quick and dirty way. 107 ******************************************************************************/ 108 void arm_bl2_plat_arch_setup(void) 109 { 110 #if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG 111 /* 112 * Ensure ARM platforms don't use coherent memory in BL2 unless 113 * cryptocell integration is enabled. 114 */ 115 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); 116 #endif 117 118 const mmap_region_t bl_regions[] = { 119 MAP_BL2_TOTAL, 120 ARM_MAP_BL_RO, 121 #if USE_ROMLIB 122 ARM_MAP_ROMLIB_CODE, 123 ARM_MAP_ROMLIB_DATA, 124 #endif 125 #if ARM_CRYPTOCELL_INTEG 126 ARM_MAP_BL_COHERENT_RAM, 127 #endif 128 {0} 129 }; 130 131 setup_page_tables(bl_regions, plat_arm_get_mmap()); 132 133 #ifdef AARCH32 134 enable_mmu_svc_mon(0); 135 #else 136 enable_mmu_el1(0); 137 #endif 138 139 arm_setup_romlib(); 140 } 141 142 void bl2_plat_arch_setup(void) 143 { 144 arm_bl2_plat_arch_setup(); 145 } 146 147 int arm_bl2_handle_post_image_load(unsigned int image_id) 148 { 149 int err = 0; 150 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 151 #ifdef SPD_opteed 152 bl_mem_params_node_t *pager_mem_params = NULL; 153 bl_mem_params_node_t *paged_mem_params = NULL; 154 #endif 155 assert(bl_mem_params); 156 157 switch (image_id) { 158 #ifdef AARCH64 159 case BL32_IMAGE_ID: 160 #ifdef SPD_opteed 161 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 162 assert(pager_mem_params); 163 164 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 165 assert(paged_mem_params); 166 167 err = parse_optee_header(&bl_mem_params->ep_info, 168 &pager_mem_params->image_info, 169 &paged_mem_params->image_info); 170 if (err != 0) { 171 WARN("OPTEE header parse error.\n"); 172 } 173 #endif 174 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry(); 175 break; 176 #endif 177 178 case BL33_IMAGE_ID: 179 /* BL33 expects to receive the primary CPU MPID (through r0) */ 180 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 181 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry(); 182 break; 183 184 #ifdef SCP_BL2_BASE 185 case SCP_BL2_IMAGE_ID: 186 /* The subsequent handling of SCP_BL2 is platform specific */ 187 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info); 188 if (err) { 189 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 190 } 191 break; 192 #endif 193 default: 194 /* Do nothing in default case */ 195 break; 196 } 197 198 return err; 199 } 200 201 /******************************************************************************* 202 * This function can be used by the platforms to update/use image 203 * information for given `image_id`. 204 ******************************************************************************/ 205 int arm_bl2_plat_handle_post_image_load(unsigned int image_id) 206 { 207 return arm_bl2_handle_post_image_load(image_id); 208 } 209 210 int bl2_plat_handle_post_image_load(unsigned int image_id) 211 { 212 return arm_bl2_plat_handle_post_image_load(image_id); 213 } 214