1 /* 2 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <bl31_param.h> 12 #include <common_def.h> 13 #include <rk3399_def.h> 14 #include <utils_def.h> 15 16 /******************************************************************************* 17 * Platform binary types for linking 18 ******************************************************************************/ 19 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 20 #define PLATFORM_LINKER_ARCH aarch64 21 22 /******************************************************************************* 23 * Generic platform constants 24 ******************************************************************************/ 25 26 /* Size of cacheable stacks */ 27 #if defined(IMAGE_BL1) 28 #define PLATFORM_STACK_SIZE 0x440 29 #elif defined(IMAGE_BL2) 30 #define PLATFORM_STACK_SIZE 0x400 31 #elif defined(IMAGE_BL31) 32 #define PLATFORM_STACK_SIZE 0x800 33 #elif defined(IMAGE_BL32) 34 #define PLATFORM_STACK_SIZE 0x440 35 #endif 36 37 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 38 39 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 40 #define PLATFORM_SYSTEM_COUNT 1 41 #define PLATFORM_CLUSTER_COUNT 2 42 #define PLATFORM_CLUSTER0_CORE_COUNT 4 43 #define PLATFORM_CLUSTER1_CORE_COUNT 2 44 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 45 PLATFORM_CLUSTER0_CORE_COUNT) 46 #define PLATFORM_MAX_CPUS_PER_CLUSTER 4 47 #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ 48 PLATFORM_CLUSTER_COUNT + \ 49 PLATFORM_CORE_COUNT) 50 #define PLAT_RK_CLST_TO_CPUID_SHIFT 6 51 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 52 53 /* 54 * This macro defines the deepest retention state possible. A higher state 55 * id will represent an invalid or a power down state. 56 */ 57 #define PLAT_MAX_RET_STATE U(1) 58 59 /* 60 * This macro defines the deepest power down states possible. Any state ID 61 * higher than this is invalid. 62 */ 63 #define PLAT_MAX_OFF_STATE U(2) 64 65 /******************************************************************************* 66 * Platform specific page table and MMU setup constants 67 ******************************************************************************/ 68 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 69 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 70 #define MAX_XLAT_TABLES 20 71 #define MAX_MMAP_REGIONS 25 72 73 /******************************************************************************* 74 * Declarations and constants to access the mailboxes safely. Each mailbox is 75 * aligned on the biggest cache line size in the platform. This is known only 76 * to the platform as it might have a combination of integrated and external 77 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 78 * line at any cache level. They could belong to different cpus/clusters & 79 * get written while being protected by different locks causing corruption of 80 * a valid mailbox address. 81 ******************************************************************************/ 82 #define CACHE_WRITEBACK_SHIFT 6 83 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 84 85 /* 86 * Define GICD and GICC and GICR base 87 */ 88 #define PLAT_RK_GICD_BASE BASE_GICD_BASE 89 #define PLAT_RK_GICR_BASE BASE_GICR_BASE 90 #define PLAT_RK_GICC_BASE 0 91 92 #define PLAT_RK_UART_BASE UART2_BASE 93 #define PLAT_RK_UART_CLOCK RK3399_UART_CLOCK 94 #define PLAT_RK_UART_BAUDRATE RK3399_BAUDRATE 95 96 #define PLAT_RK_CCI_BASE CCI500_BASE 97 98 #define PLAT_RK_PRIMARY_CPU 0x0 99 100 #define PSRAM_DO_DDR_RESUME 1 101 #define PSRAM_CHECK_WAKEUP_CPU 0 102 103 #endif /* PLATFORM_DEF_H */ 104