1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 /* CCU unit device driver for Marvell AP807, AP807 and AP810 SoCs */ 9 10 #include <common/debug.h> 11 #include <drivers/marvell/ccu.h> 12 #include <lib/mmio.h> 13 14 #include <armada_common.h> 15 #include <mvebu.h> 16 #include <mvebu_def.h> 17 18 #if LOG_LEVEL >= LOG_LEVEL_INFO 19 #define DEBUG_ADDR_MAP 20 #endif 21 22 /* common defines */ 23 #define WIN_ENABLE_BIT (0x1) 24 /* Physical address of the base of the window = {AddrLow[19:0],20'h0} */ 25 #define ADDRESS_SHIFT (20 - 4) 26 #define ADDRESS_MASK (0xFFFFFFF0) 27 #define CCU_WIN_ALIGNMENT (0x100000) 28 29 #define IS_DRAM_TARGET(tgt) ((((tgt) == DRAM_0_TID) || \ 30 ((tgt) == DRAM_1_TID) || \ 31 ((tgt) == RAR_TID)) ? 1 : 0) 32 33 /* For storage of CR, SCR, ALR, AHR abd GCR */ 34 static uint32_t ccu_regs_save[MVEBU_CCU_MAX_WINS * 4 + 1]; 35 36 #ifdef DEBUG_ADDR_MAP 37 static void dump_ccu(int ap_index) 38 { 39 uint32_t win_id, win_cr, alr, ahr; 40 uint8_t target_id; 41 uint64_t start, end; 42 43 /* Dump all AP windows */ 44 printf("\tbank target start end\n"); 45 printf("\t----------------------------------------------------\n"); 46 for (win_id = 0; win_id < MVEBU_CCU_MAX_WINS; win_id++) { 47 win_cr = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); 48 if (win_cr & WIN_ENABLE_BIT) { 49 target_id = (win_cr >> CCU_TARGET_ID_OFFSET) & 50 CCU_TARGET_ID_MASK; 51 alr = mmio_read_32(CCU_WIN_ALR_OFFSET(ap_index, 52 win_id)); 53 ahr = mmio_read_32(CCU_WIN_AHR_OFFSET(ap_index, 54 win_id)); 55 start = ((uint64_t)alr << ADDRESS_SHIFT); 56 end = (((uint64_t)ahr + 0x10) << ADDRESS_SHIFT); 57 printf("\tccu %02x 0x%016llx 0x%016llx\n", 58 target_id, start, end); 59 } 60 } 61 win_cr = mmio_read_32(CCU_WIN_GCR_OFFSET(ap_index)); 62 target_id = (win_cr >> CCU_GCR_TARGET_OFFSET) & CCU_GCR_TARGET_MASK; 63 printf("\tccu GCR %d - all other transactions\n", target_id); 64 } 65 #endif 66 67 void ccu_win_check(struct addr_map_win *win) 68 { 69 /* check if address is aligned to 1M */ 70 if (IS_NOT_ALIGN(win->base_addr, CCU_WIN_ALIGNMENT)) { 71 win->base_addr = ALIGN_UP(win->base_addr, CCU_WIN_ALIGNMENT); 72 NOTICE("%s: Align up the base address to 0x%llx\n", 73 __func__, win->base_addr); 74 } 75 76 /* size parameter validity check */ 77 if (IS_NOT_ALIGN(win->win_size, CCU_WIN_ALIGNMENT)) { 78 win->win_size = ALIGN_UP(win->win_size, CCU_WIN_ALIGNMENT); 79 NOTICE("%s: Aligning size to 0x%llx\n", 80 __func__, win->win_size); 81 } 82 } 83 84 void ccu_enable_win(int ap_index, struct addr_map_win *win, uint32_t win_id) 85 { 86 uint32_t ccu_win_reg; 87 uint32_t alr, ahr; 88 uint64_t end_addr; 89 90 if ((win_id == 0) || (win_id > MVEBU_CCU_MAX_WINS)) { 91 ERROR("Enabling wrong CCU window %d!\n", win_id); 92 return; 93 } 94 95 end_addr = (win->base_addr + win->win_size - 1); 96 alr = (uint32_t)((win->base_addr >> ADDRESS_SHIFT) & ADDRESS_MASK); 97 ahr = (uint32_t)((end_addr >> ADDRESS_SHIFT) & ADDRESS_MASK); 98 99 mmio_write_32(CCU_WIN_ALR_OFFSET(ap_index, win_id), alr); 100 mmio_write_32(CCU_WIN_AHR_OFFSET(ap_index, win_id), ahr); 101 102 ccu_win_reg = WIN_ENABLE_BIT; 103 ccu_win_reg |= (win->target_id & CCU_TARGET_ID_MASK) 104 << CCU_TARGET_ID_OFFSET; 105 mmio_write_32(CCU_WIN_CR_OFFSET(ap_index, win_id), ccu_win_reg); 106 } 107 108 static void ccu_disable_win(int ap_index, uint32_t win_id) 109 { 110 uint32_t win_reg; 111 112 if ((win_id == 0) || (win_id > MVEBU_CCU_MAX_WINS)) { 113 ERROR("Disabling wrong CCU window %d!\n", win_id); 114 return; 115 } 116 117 win_reg = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); 118 win_reg &= ~WIN_ENABLE_BIT; 119 mmio_write_32(CCU_WIN_CR_OFFSET(ap_index, win_id), win_reg); 120 } 121 122 /* Insert/Remove temporary window for using the out-of reset default 123 * CPx base address to access the CP configuration space prior to 124 * the further base address update in accordance with address mapping 125 * design. 126 * 127 * NOTE: Use the same window array for insertion and removal of 128 * temporary windows. 129 */ 130 void ccu_temp_win_insert(int ap_index, struct addr_map_win *win, int size) 131 { 132 uint32_t win_id; 133 134 for (int i = 0; i < size; i++) { 135 win_id = MVEBU_CCU_MAX_WINS - 1 - i; 136 ccu_win_check(win); 137 ccu_enable_win(ap_index, win, win_id); 138 win++; 139 } 140 } 141 142 /* 143 * NOTE: Use the same window array for insertion and removal of 144 * temporary windows. 145 */ 146 void ccu_temp_win_remove(int ap_index, struct addr_map_win *win, int size) 147 { 148 uint32_t win_id; 149 150 for (int i = 0; i < size; i++) { 151 uint64_t base; 152 uint32_t target; 153 154 win_id = MVEBU_CCU_MAX_WINS - 1 - i; 155 156 target = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); 157 target >>= CCU_TARGET_ID_OFFSET; 158 target &= CCU_TARGET_ID_MASK; 159 160 base = mmio_read_32(CCU_WIN_ALR_OFFSET(ap_index, win_id)); 161 base <<= ADDRESS_SHIFT; 162 163 if ((win->target_id != target) || (win->base_addr != base)) { 164 ERROR("%s: Trying to remove bad window-%d!\n", 165 __func__, win_id); 166 continue; 167 } 168 ccu_disable_win(ap_index, win_id); 169 win++; 170 } 171 } 172 173 /* Returns current DRAM window target (DRAM_0_TID, DRAM_1_TID, RAR_TID) 174 * NOTE: Call only once for each AP. 175 * The AP0 DRAM window is located at index 2 only at the BL31 execution start. 176 * Then it relocated to index 1 for matching the rest of APs DRAM settings. 177 * Calling this function after relocation will produce wrong results on AP0 178 */ 179 static uint32_t ccu_dram_target_get(int ap_index) 180 { 181 /* On BLE stage the AP0 DRAM window is opened by the BootROM at index 2. 182 * All the rest of detected APs will use window at index 1. 183 * The AP0 DRAM window is moved from index 2 to 1 during 184 * init_ccu() execution. 185 */ 186 const uint32_t win_id = (ap_index == 0) ? 2 : 1; 187 uint32_t target; 188 189 target = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); 190 target >>= CCU_TARGET_ID_OFFSET; 191 target &= CCU_TARGET_ID_MASK; 192 193 return target; 194 } 195 196 void ccu_dram_target_set(int ap_index, uint32_t target) 197 { 198 /* On BLE stage the AP0 DRAM window is opened by the BootROM at index 2. 199 * All the rest of detected APs will use window at index 1. 200 * The AP0 DRAM window is moved from index 2 to 1 201 * during init_ccu() execution. 202 */ 203 const uint32_t win_id = (ap_index == 0) ? 2 : 1; 204 uint32_t dram_cr; 205 206 dram_cr = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); 207 dram_cr &= ~(CCU_TARGET_ID_MASK << CCU_TARGET_ID_OFFSET); 208 dram_cr |= (target & CCU_TARGET_ID_MASK) << CCU_TARGET_ID_OFFSET; 209 mmio_write_32(CCU_WIN_CR_OFFSET(ap_index, win_id), dram_cr); 210 } 211 212 /* Setup CCU DRAM window and enable it */ 213 void ccu_dram_win_config(int ap_index, struct addr_map_win *win) 214 { 215 #if IMAGE_BLE /* BLE */ 216 /* On BLE stage the AP0 DRAM window is opened by the BootROM at index 2. 217 * Since the BootROM is not accessing DRAM at BLE stage, 218 * the DRAM window can be temporarely disabled. 219 */ 220 const uint32_t win_id = (ap_index == 0) ? 2 : 1; 221 #else /* end of BLE */ 222 /* At the ccu_init() execution stage, DRAM windows of all APs 223 * are arranged at index 1. 224 * The AP0 still has the old window BootROM DRAM at index 2, so 225 * the window-1 can be safely disabled without breaking the DRAM access. 226 */ 227 const uint32_t win_id = 1; 228 #endif 229 230 ccu_disable_win(ap_index, win_id); 231 /* enable write secure (and clear read secure) */ 232 mmio_write_32(CCU_WIN_SCR_OFFSET(ap_index, win_id), 233 CCU_WIN_ENA_WRITE_SECURE); 234 ccu_win_check(win); 235 ccu_enable_win(ap_index, win, win_id); 236 } 237 238 /* Save content of CCU window + GCR */ 239 static void ccu_save_win_range(int ap_id, int win_first, 240 int win_last, uint32_t *buffer) 241 { 242 int win_id, idx; 243 /* Save CCU */ 244 for (idx = 0, win_id = win_first; win_id <= win_last; win_id++) { 245 buffer[idx++] = mmio_read_32(CCU_WIN_CR_OFFSET(ap_id, win_id)); 246 buffer[idx++] = mmio_read_32(CCU_WIN_SCR_OFFSET(ap_id, win_id)); 247 buffer[idx++] = mmio_read_32(CCU_WIN_ALR_OFFSET(ap_id, win_id)); 248 buffer[idx++] = mmio_read_32(CCU_WIN_AHR_OFFSET(ap_id, win_id)); 249 } 250 buffer[idx] = mmio_read_32(CCU_WIN_GCR_OFFSET(ap_id)); 251 } 252 253 /* Restore content of CCU window + GCR */ 254 static void ccu_restore_win_range(int ap_id, int win_first, 255 int win_last, uint32_t *buffer) 256 { 257 int win_id, idx; 258 /* Restore CCU */ 259 for (idx = 0, win_id = win_first; win_id <= win_last; win_id++) { 260 mmio_write_32(CCU_WIN_CR_OFFSET(ap_id, win_id), buffer[idx++]); 261 mmio_write_32(CCU_WIN_SCR_OFFSET(ap_id, win_id), buffer[idx++]); 262 mmio_write_32(CCU_WIN_ALR_OFFSET(ap_id, win_id), buffer[idx++]); 263 mmio_write_32(CCU_WIN_AHR_OFFSET(ap_id, win_id), buffer[idx++]); 264 } 265 mmio_write_32(CCU_WIN_GCR_OFFSET(ap_id), buffer[idx]); 266 } 267 268 void ccu_save_win_all(int ap_id) 269 { 270 ccu_save_win_range(ap_id, 0, MVEBU_CCU_MAX_WINS - 1, ccu_regs_save); 271 } 272 273 void ccu_restore_win_all(int ap_id) 274 { 275 ccu_restore_win_range(ap_id, 0, MVEBU_CCU_MAX_WINS - 1, ccu_regs_save); 276 } 277 278 int init_ccu(int ap_index) 279 { 280 struct addr_map_win *win, *dram_win; 281 uint32_t win_id, win_reg; 282 uint32_t win_count, array_id; 283 uint32_t dram_target; 284 #if IMAGE_BLE 285 /* In BootROM context CCU Window-1 286 * has SRAM_TID target and should not be disabled 287 */ 288 const uint32_t win_start = 2; 289 #else 290 const uint32_t win_start = 1; 291 #endif 292 293 INFO("Initializing CCU Address decoding\n"); 294 295 /* Get the array of the windows and fill the map data */ 296 marvell_get_ccu_memory_map(ap_index, &win, &win_count); 297 if (win_count <= 0) { 298 INFO("No windows configurations found\n"); 299 } else if (win_count > (MVEBU_CCU_MAX_WINS - 1)) { 300 ERROR("CCU mem map array > than max available windows (%d)\n", 301 MVEBU_CCU_MAX_WINS); 302 win_count = MVEBU_CCU_MAX_WINS; 303 } 304 305 /* Need to set GCR to DRAM before all CCU windows are disabled for 306 * securing the normal access to DRAM location, which the ATF is running 307 * from. Once all CCU windows are set, which have to include the 308 * dedicated DRAM window as well, the GCR can be switched to the target 309 * defined by the platform configuration. 310 */ 311 dram_target = ccu_dram_target_get(ap_index); 312 win_reg = (dram_target & CCU_GCR_TARGET_MASK) << CCU_GCR_TARGET_OFFSET; 313 mmio_write_32(CCU_WIN_GCR_OFFSET(ap_index), win_reg); 314 315 /* If the DRAM window was already configured at the BLE stage, 316 * only the window target considered valid, the address range should be 317 * updated according to the platform configuration. 318 */ 319 for (dram_win = win, array_id = 0; array_id < win_count; 320 array_id++, dram_win++) { 321 if (IS_DRAM_TARGET(dram_win->target_id)) { 322 dram_win->target_id = dram_target; 323 break; 324 } 325 } 326 327 /* Disable all AP CCU windows 328 * Window-0 is always bypassed since it already contains 329 * data allowing the internal configuration space access 330 */ 331 for (win_id = win_start; win_id < MVEBU_CCU_MAX_WINS; win_id++) { 332 ccu_disable_win(ap_index, win_id); 333 /* enable write secure (and clear read secure) */ 334 mmio_write_32(CCU_WIN_SCR_OFFSET(ap_index, win_id), 335 CCU_WIN_ENA_WRITE_SECURE); 336 } 337 338 /* win_id is the index of the current ccu window 339 * array_id is the index of the current memory map window entry 340 */ 341 for (win_id = win_start, array_id = 0; 342 ((win_id < MVEBU_CCU_MAX_WINS) && (array_id < win_count)); 343 win_id++) { 344 ccu_win_check(win); 345 ccu_enable_win(ap_index, win, win_id); 346 win++; 347 array_id++; 348 } 349 350 /* Get & set the default target according to board topology */ 351 win_reg = (marvell_get_ccu_gcr_target(ap_index) & CCU_GCR_TARGET_MASK) 352 << CCU_GCR_TARGET_OFFSET; 353 mmio_write_32(CCU_WIN_GCR_OFFSET(ap_index), win_reg); 354 355 #ifdef DEBUG_ADDR_MAP 356 dump_ccu(ap_index); 357 #endif 358 359 INFO("Done CCU Address decoding Initializing\n"); 360 361 return 0; 362 } 363