1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <common_def.h> 12 #include <gic_common.h> 13 #include <utils_def.h> 14 #include "../stm32mp1_def.h" 15 16 /******************************************************************************* 17 * Generic platform constants 18 ******************************************************************************/ 19 20 /* Size of cacheable stacks */ 21 #if defined(IMAGE_BL32) 22 #define PLATFORM_STACK_SIZE 0x600 23 #else 24 #define PLATFORM_STACK_SIZE 0xC00 25 #endif 26 27 /* SSBL = second stage boot loader */ 28 #define BL33_IMAGE_NAME "ssbl" 29 #define BL33_BINARY_TYPE U(0x0) 30 31 #define STM32MP1_PRIMARY_CPU U(0x0) 32 33 #define PLATFORM_CACHE_LINE_SIZE 64 34 #define PLATFORM_CLUSTER_COUNT ULL(1) 35 #define PLATFORM_CLUSTER0_CORE_COUNT U(2) 36 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 37 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 38 PLATFORM_CLUSTER0_CORE_COUNT) 39 #define PLATFORM_MAX_CPUS_PER_CLUSTER 2 40 41 #define MAX_IO_DEVICES 4 42 #define MAX_IO_HANDLES 4 43 #define MAX_IO_BLOCK_DEVICES 1 44 45 /******************************************************************************* 46 * BL2 specific defines. 47 ******************************************************************************/ 48 /* 49 * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug 50 * size plus a little space for growth. 51 */ 52 #define BL2_BASE STM32MP1_BL2_BASE 53 #define BL2_LIMIT (STM32MP1_BL2_BASE + \ 54 STM32MP1_BL2_SIZE) 55 56 /******************************************************************************* 57 * BL32 specific defines. 58 ******************************************************************************/ 59 #define BL32_BASE STM32MP1_BL32_BASE 60 #define BL32_LIMIT (STM32MP1_BL32_BASE + \ 61 STM32MP1_BL32_SIZE) 62 63 /******************************************************************************* 64 * BL33 specific defines. 65 ******************************************************************************/ 66 #define BL33_BASE STM32MP1_BL33_BASE 67 68 /* 69 * Load address of BL33 for this platform port 70 */ 71 #define PLAT_STM32MP1_NS_IMAGE_OFFSET BL33_BASE 72 73 /******************************************************************************* 74 * DTB specific defines. 75 ******************************************************************************/ 76 #define DTB_BASE STM32MP1_DTB_BASE 77 #define DTB_LIMIT (STM32MP1_DTB_BASE + \ 78 STM32MP1_DTB_SIZE) 79 80 /******************************************************************************* 81 * Platform specific page table and MMU setup constants 82 ******************************************************************************/ 83 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 84 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 85 86 /******************************************************************************* 87 * Declarations and constants to access the mailboxes safely. Each mailbox is 88 * aligned on the biggest cache line size in the platform. This is known only 89 * to the platform as it might have a combination of integrated and external 90 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 91 * line at any cache level. They could belong to different cpus/clusters & 92 * get written while being protected by different locks causing corruption of 93 * a valid mailbox address. 94 ******************************************************************************/ 95 #define CACHE_WRITEBACK_SHIFT 6 96 #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 97 98 /* 99 * Secure Interrupt: based on the standard ARM mapping 100 */ 101 #define ARM_IRQ_SEC_PHY_TIMER U(29) 102 103 #define ARM_IRQ_SEC_SGI_0 U(8) 104 #define ARM_IRQ_SEC_SGI_1 U(9) 105 #define ARM_IRQ_SEC_SGI_2 U(10) 106 #define ARM_IRQ_SEC_SGI_3 U(11) 107 #define ARM_IRQ_SEC_SGI_4 U(12) 108 #define ARM_IRQ_SEC_SGI_5 U(13) 109 #define ARM_IRQ_SEC_SGI_6 U(14) 110 #define ARM_IRQ_SEC_SGI_7 U(15) 111 112 #define STM32MP1_IRQ_TZC400 U(36) 113 #define STM32MP1_IRQ_TAMPSERRS U(229) 114 #define STM32MP1_IRQ_AXIERRIRQ U(244) 115 116 /* 117 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 118 * terminology. On a GICv2 system or mode, the lists will be merged and treated 119 * as Group 0 interrupts. 120 */ 121 #define PLATFORM_G1S_PROPS(grp) \ 122 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, \ 123 GIC_HIGHEST_SEC_PRIORITY, \ 124 grp, GIC_INTR_CFG_LEVEL), \ 125 INTR_PROP_DESC(STM32MP1_IRQ_TAMPSERRS, \ 126 GIC_HIGHEST_SEC_PRIORITY, \ 127 grp, GIC_INTR_CFG_LEVEL), \ 128 INTR_PROP_DESC(STM32MP1_IRQ_AXIERRIRQ, \ 129 GIC_HIGHEST_SEC_PRIORITY, \ 130 grp, GIC_INTR_CFG_LEVEL), \ 131 INTR_PROP_DESC(STM32MP1_IRQ_TZC400, \ 132 GIC_HIGHEST_SEC_PRIORITY, \ 133 grp, GIC_INTR_CFG_LEVEL), \ 134 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, \ 135 GIC_HIGHEST_SEC_PRIORITY, \ 136 grp, GIC_INTR_CFG_EDGE), \ 137 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, \ 138 GIC_HIGHEST_SEC_PRIORITY, \ 139 grp, GIC_INTR_CFG_EDGE), \ 140 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, \ 141 GIC_HIGHEST_SEC_PRIORITY, \ 142 grp, GIC_INTR_CFG_EDGE), \ 143 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, \ 144 GIC_HIGHEST_SEC_PRIORITY, \ 145 grp, GIC_INTR_CFG_EDGE), \ 146 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, \ 147 GIC_HIGHEST_SEC_PRIORITY, \ 148 grp, GIC_INTR_CFG_EDGE), \ 149 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, \ 150 GIC_HIGHEST_SEC_PRIORITY, \ 151 grp, GIC_INTR_CFG_EDGE) 152 153 #define PLATFORM_G0_PROPS(grp) \ 154 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, \ 155 GIC_HIGHEST_SEC_PRIORITY, \ 156 grp, GIC_INTR_CFG_EDGE), \ 157 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, \ 158 GIC_HIGHEST_SEC_PRIORITY, \ 159 grp, GIC_INTR_CFG_EDGE) 160 161 /* 162 * Power 163 */ 164 #define PLAT_MAX_PWR_LVL U(1) 165 166 /* Local power state for power domains in Run state. */ 167 #define ARM_LOCAL_STATE_RUN U(0) 168 /* Local power state for retention. Valid only for CPU power domains */ 169 #define ARM_LOCAL_STATE_RET U(1) 170 /* Local power state for power-down. Valid for CPU and cluster power domains */ 171 #define ARM_LOCAL_STATE_OFF U(2) 172 /* 173 * This macro defines the deepest retention state possible. 174 * A higher state id will represent an invalid or a power down state. 175 */ 176 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 177 /* 178 * This macro defines the deepest power down states possible. Any state ID 179 * higher than this is invalid. 180 */ 181 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 182 183 /******************************************************************************* 184 * Size of the per-cpu data in bytes that should be reserved in the generic 185 * per-cpu data structure for the FVP port. 186 ******************************************************************************/ 187 #define PLAT_PCPU_DATA_SIZE 2 188 189 #endif /* PLATFORM_DEF_H */ 190