1/* 2 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10 11 .globl bl2_vector_table 12 .globl bl2_entrypoint 13 14 15vector_base bl2_vector_table 16 b bl2_entrypoint 17 b report_exception /* Undef */ 18 b report_exception /* SVC call */ 19 b report_exception /* Prefetch abort */ 20 b report_exception /* Data abort */ 21 b report_exception /* Reserved */ 22 b report_exception /* IRQ */ 23 b report_exception /* FIQ */ 24 25 26func bl2_entrypoint 27 /*--------------------------------------------- 28 * Save arguments x0 - x3 from BL1 for future 29 * use. 30 * --------------------------------------------- 31 */ 32 mov r9, r0 33 mov r10, r1 34 mov r11, r2 35 mov r12, r3 36 37 /* --------------------------------------------- 38 * Set the exception vector to something sane. 39 * --------------------------------------------- 40 */ 41 ldr r0, =bl2_vector_table 42 stcopr r0, VBAR 43 isb 44 45 /* ----------------------------------------------------- 46 * Enable the instruction cache 47 * ----------------------------------------------------- 48 */ 49 ldcopr r0, SCTLR 50 orr r0, r0, #SCTLR_I_BIT 51 stcopr r0, SCTLR 52 isb 53 54 /* --------------------------------------------- 55 * Since BL2 executes after BL1, it is assumed 56 * here that BL1 has already has done the 57 * necessary register initializations. 58 * --------------------------------------------- 59 */ 60 61 /* --------------------------------------------- 62 * Invalidate the RW memory used by the BL2 63 * image. This includes the data and NOBITS 64 * sections. This is done to safeguard against 65 * possible corruption of this memory by dirty 66 * cache lines in a system cache as a result of 67 * use by an earlier boot loader stage. 68 * --------------------------------------------- 69 */ 70 ldr r0, =__RW_START__ 71 ldr r1, =__RW_END__ 72 sub r1, r1, r0 73 bl inv_dcache_range 74 75 /* --------------------------------------------- 76 * Zero out NOBITS sections. There are 2 of them: 77 * - the .bss section; 78 * - the coherent memory section. 79 * --------------------------------------------- 80 */ 81 ldr r0, =__BSS_START__ 82 ldr r1, =__BSS_SIZE__ 83 bl zeromem 84 85#if USE_COHERENT_MEM 86 ldr r0, =__COHERENT_RAM_START__ 87 ldr r1, =__COHERENT_RAM_UNALIGNED_SIZE__ 88 bl zeromem 89#endif 90 91 /* -------------------------------------------- 92 * Allocate a stack whose memory will be marked 93 * as Normal-IS-WBWA when the MMU is enabled. 94 * There is no risk of reading stale stack 95 * memory after enabling the MMU as only the 96 * primary cpu is running at the moment. 97 * -------------------------------------------- 98 */ 99 bl plat_set_my_stack 100 101 /* --------------------------------------------- 102 * Initialize the stack protector canary before 103 * any C code is called. 104 * --------------------------------------------- 105 */ 106#if STACK_PROTECTOR_ENABLED 107 bl update_stack_protector_canary 108#endif 109 110 /* --------------------------------------------- 111 * Perform early platform setup & platform 112 * specific early arch. setup e.g. mmu setup 113 * --------------------------------------------- 114 */ 115 mov r0, r9 116 mov r1, r10 117 mov r2, r11 118 mov r3, r12 119 bl bl2_early_platform_setup2 120 bl bl2_plat_arch_setup 121 122 /* --------------------------------------------- 123 * Jump to main function. 124 * --------------------------------------------- 125 */ 126 bl bl2_main 127 128 /* --------------------------------------------- 129 * Should never reach this point. 130 * --------------------------------------------- 131 */ 132 no_ret plat_panic_handler 133 134endfunc bl2_entrypoint 135