1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_A72_H 8 #define CORTEX_A72_H 9 #include <utils_def.h> 10 11 /* Cortex-A72 midr for revision 0 */ 12 #define CORTEX_A72_MIDR 0x410FD080 13 14 /******************************************************************************* 15 * CPU Extended Control register specific definitions. 16 ******************************************************************************/ 17 #define CORTEX_A72_ECTLR p15, 1, c15 18 19 #define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6) 20 #define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38) 21 #define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35) 22 #define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32) 23 24 /******************************************************************************* 25 * CPU Memory Error Syndrome register specific definitions. 26 ******************************************************************************/ 27 #define CORTEX_A72_MERRSR p15, 2, c15 28 29 /******************************************************************************* 30 * CPU Auxiliary Control register specific definitions. 31 ******************************************************************************/ 32 #define CORTEX_A72_CPUACTLR p15, 0, c15 33 34 #define CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56) 35 #define CORTEX_A72_CPUACTLR_DIS_LOAD_PASS_STORE (ULL(1) << 55) 36 #define CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49) 37 #define CORTEX_A72_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44) 38 #define CORTEX_A72_CPUACTLR_DIS_INSTR_PREFETCH (ULL(1) << 32) 39 40 /******************************************************************************* 41 * L2 Control register specific definitions. 42 ******************************************************************************/ 43 #define CORTEX_A72_L2CTLR p15, 1, c9, c0, 2 44 45 #define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0 46 #define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6 47 48 #define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 0x2 49 #define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 0x1 50 #define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 0x2 51 52 /******************************************************************************* 53 * L2 Memory Error Syndrome register specific definitions. 54 ******************************************************************************/ 55 #define CORTEX_A72_L2MERRSR p15, 3, c15 56 57 #endif /* CORTEX_A72_H */ 58