1 /* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <common/debug.h> 10 #include <drivers/arm/cci.h> 11 #include <drivers/arm/ccn.h> 12 #include <drivers/arm/gicv2.h> 13 #include <lib/mmio.h> 14 #include <lib/xlat_tables/xlat_tables_compat.h> 15 #include <plat/common/platform.h> 16 #include <services/secure_partition.h> 17 18 #include <arm_config.h> 19 #include <arm_def.h> 20 #include <arm_spm_def.h> 21 #include <plat_arm.h> 22 #include <v2m_def.h> 23 24 #include "../fvp_def.h" 25 #include "fvp_private.h" 26 27 /* Defines for GIC Driver build time selection */ 28 #define FVP_GICV2 1 29 #define FVP_GICV3 2 30 31 /******************************************************************************* 32 * arm_config holds the characteristics of the differences between the three FVP 33 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot 34 * at each boot stage by the primary before enabling the MMU (to allow 35 * interconnect configuration) & used thereafter. Each BL will have its own copy 36 * to allow independent operation. 37 ******************************************************************************/ 38 arm_config_t arm_config; 39 40 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 41 DEVICE0_SIZE, \ 42 MT_DEVICE | MT_RW | MT_SECURE) 43 44 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ 45 DEVICE1_SIZE, \ 46 MT_DEVICE | MT_RW | MT_SECURE) 47 48 /* 49 * Need to be mapped with write permissions in order to set a new non-volatile 50 * counter value. 51 */ 52 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ 53 DEVICE2_SIZE, \ 54 MT_DEVICE | MT_RW | MT_SECURE) 55 56 /* 57 * Table of memory regions for various BL stages to map using the MMU. 58 * This doesn't include Trusted SRAM as setup_page_tables() already takes care 59 * of mapping it. 60 * 61 * The flash needs to be mapped as writable in order to erase the FIP's Table of 62 * Contents in case of unrecoverable error (see plat_error_handler()). 63 */ 64 #ifdef IMAGE_BL1 65 const mmap_region_t plat_arm_mmap[] = { 66 ARM_MAP_SHARED_RAM, 67 V2M_MAP_FLASH0_RW, 68 V2M_MAP_IOFPGA, 69 MAP_DEVICE0, 70 MAP_DEVICE1, 71 #if TRUSTED_BOARD_BOOT 72 /* To access the Root of Trust Public Key registers. */ 73 MAP_DEVICE2, 74 /* Map DRAM to authenticate NS_BL2U image. */ 75 ARM_MAP_NS_DRAM1, 76 #endif 77 {0} 78 }; 79 #endif 80 #ifdef IMAGE_BL2 81 const mmap_region_t plat_arm_mmap[] = { 82 ARM_MAP_SHARED_RAM, 83 V2M_MAP_FLASH0_RW, 84 V2M_MAP_IOFPGA, 85 MAP_DEVICE0, 86 MAP_DEVICE1, 87 ARM_MAP_NS_DRAM1, 88 #ifdef AARCH64 89 ARM_MAP_DRAM2, 90 #endif 91 #ifdef SPD_tspd 92 ARM_MAP_TSP_SEC_MEM, 93 #endif 94 #if TRUSTED_BOARD_BOOT 95 /* To access the Root of Trust Public Key registers. */ 96 MAP_DEVICE2, 97 #if !BL2_AT_EL3 98 ARM_MAP_BL1_RW, 99 #endif 100 #endif /* TRUSTED_BOARD_BOOT */ 101 #if ENABLE_SPM && SPM_DEPRECATED 102 ARM_SP_IMAGE_MMAP, 103 #endif 104 #if ENABLE_SPM && !SPM_DEPRECATED 105 PLAT_MAP_SP_PACKAGE_MEM_RW, 106 #endif 107 #if ARM_BL31_IN_DRAM 108 ARM_MAP_BL31_SEC_DRAM, 109 #endif 110 #ifdef SPD_opteed 111 ARM_MAP_OPTEE_CORE_MEM, 112 ARM_OPTEE_PAGEABLE_LOAD_MEM, 113 #endif 114 {0} 115 }; 116 #endif 117 #ifdef IMAGE_BL2U 118 const mmap_region_t plat_arm_mmap[] = { 119 MAP_DEVICE0, 120 V2M_MAP_IOFPGA, 121 {0} 122 }; 123 #endif 124 #ifdef IMAGE_BL31 125 const mmap_region_t plat_arm_mmap[] = { 126 ARM_MAP_SHARED_RAM, 127 ARM_MAP_EL3_TZC_DRAM, 128 V2M_MAP_IOFPGA, 129 MAP_DEVICE0, 130 MAP_DEVICE1, 131 ARM_V2M_MAP_MEM_PROTECT, 132 #if ENABLE_SPM && SPM_DEPRECATED 133 ARM_SPM_BUF_EL3_MMAP, 134 #endif 135 #if ENABLE_SPM && !SPM_DEPRECATED 136 PLAT_MAP_SP_PACKAGE_MEM_RO, 137 #endif 138 {0} 139 }; 140 141 #if ENABLE_SPM && defined(IMAGE_BL31) && SPM_DEPRECATED 142 const mmap_region_t plat_arm_secure_partition_mmap[] = { 143 V2M_MAP_IOFPGA_EL0, /* for the UART */ 144 MAP_REGION_FLAT(DEVICE0_BASE, \ 145 DEVICE0_SIZE, \ 146 MT_DEVICE | MT_RO | MT_SECURE | MT_USER), 147 ARM_SP_IMAGE_MMAP, 148 ARM_SP_IMAGE_NS_BUF_MMAP, 149 ARM_SP_IMAGE_RW_MMAP, 150 ARM_SPM_BUF_EL0_MMAP, 151 {0} 152 }; 153 #endif 154 #endif 155 #ifdef IMAGE_BL32 156 const mmap_region_t plat_arm_mmap[] = { 157 #ifdef AARCH32 158 ARM_MAP_SHARED_RAM, 159 ARM_V2M_MAP_MEM_PROTECT, 160 #endif 161 V2M_MAP_IOFPGA, 162 MAP_DEVICE0, 163 MAP_DEVICE1, 164 {0} 165 }; 166 #endif 167 168 ARM_CASSERT_MMAP 169 170 #if FVP_INTERCONNECT_DRIVER != FVP_CCN 171 static const int fvp_cci400_map[] = { 172 PLAT_FVP_CCI400_CLUS0_SL_PORT, 173 PLAT_FVP_CCI400_CLUS1_SL_PORT, 174 }; 175 176 static const int fvp_cci5xx_map[] = { 177 PLAT_FVP_CCI5XX_CLUS0_SL_PORT, 178 PLAT_FVP_CCI5XX_CLUS1_SL_PORT, 179 }; 180 181 static unsigned int get_interconnect_master(void) 182 { 183 unsigned int master; 184 u_register_t mpidr; 185 186 mpidr = read_mpidr_el1(); 187 master = ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) ? 188 MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr); 189 190 assert(master < FVP_CLUSTER_COUNT); 191 return master; 192 } 193 #endif 194 195 #if ENABLE_SPM && defined(IMAGE_BL31) && SPM_DEPRECATED 196 /* 197 * Boot information passed to a secure partition during initialisation. Linear 198 * indices in MP information will be filled at runtime. 199 */ 200 static secure_partition_mp_info_t sp_mp_info[] = { 201 [0] = {0x80000000, 0}, 202 [1] = {0x80000001, 0}, 203 [2] = {0x80000002, 0}, 204 [3] = {0x80000003, 0}, 205 [4] = {0x80000100, 0}, 206 [5] = {0x80000101, 0}, 207 [6] = {0x80000102, 0}, 208 [7] = {0x80000103, 0}, 209 }; 210 211 const secure_partition_boot_info_t plat_arm_secure_partition_boot_info = { 212 .h.type = PARAM_SP_IMAGE_BOOT_INFO, 213 .h.version = VERSION_1, 214 .h.size = sizeof(secure_partition_boot_info_t), 215 .h.attr = 0, 216 .sp_mem_base = ARM_SP_IMAGE_BASE, 217 .sp_mem_limit = ARM_SP_IMAGE_LIMIT, 218 .sp_image_base = ARM_SP_IMAGE_BASE, 219 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE, 220 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE, 221 .sp_ns_comm_buf_base = ARM_SP_IMAGE_NS_BUF_BASE, 222 .sp_shared_buf_base = PLAT_SPM_BUF_BASE, 223 .sp_image_size = ARM_SP_IMAGE_SIZE, 224 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE, 225 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE, 226 .sp_ns_comm_buf_size = ARM_SP_IMAGE_NS_BUF_SIZE, 227 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE, 228 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS, 229 .num_cpus = PLATFORM_CORE_COUNT, 230 .mp_info = &sp_mp_info[0], 231 }; 232 233 const struct mmap_region *plat_get_secure_partition_mmap(void *cookie) 234 { 235 return plat_arm_secure_partition_mmap; 236 } 237 238 const struct secure_partition_boot_info *plat_get_secure_partition_boot_info( 239 void *cookie) 240 { 241 return &plat_arm_secure_partition_boot_info; 242 } 243 #endif 244 245 /******************************************************************************* 246 * A single boot loader stack is expected to work on both the Foundation FVP 247 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The 248 * SYS_ID register provides a mechanism for detecting the differences between 249 * these platforms. This information is stored in a per-BL array to allow the 250 * code to take the correct path.Per BL platform configuration. 251 ******************************************************************************/ 252 void __init fvp_config_setup(void) 253 { 254 unsigned int rev, hbi, bld, arch, sys_id; 255 256 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 257 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK; 258 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK; 259 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK; 260 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; 261 262 if (arch != ARCH_MODEL) { 263 ERROR("This firmware is for FVP models\n"); 264 panic(); 265 } 266 267 /* 268 * The build field in the SYS_ID tells which variant of the GIC 269 * memory is implemented by the model. 270 */ 271 switch (bld) { 272 case BLD_GIC_VE_MMAP: 273 ERROR("Legacy Versatile Express memory map for GIC peripheral" 274 " is not supported\n"); 275 panic(); 276 break; 277 case BLD_GIC_A53A57_MMAP: 278 break; 279 default: 280 ERROR("Unsupported board build %x\n", bld); 281 panic(); 282 } 283 284 /* 285 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 286 * for the Foundation FVP. 287 */ 288 switch (hbi) { 289 case HBI_FOUNDATION_FVP: 290 arm_config.flags = 0; 291 292 /* 293 * Check for supported revisions of Foundation FVP 294 * Allow future revisions to run but emit warning diagnostic 295 */ 296 switch (rev) { 297 case REV_FOUNDATION_FVP_V2_0: 298 case REV_FOUNDATION_FVP_V2_1: 299 case REV_FOUNDATION_FVP_v9_1: 300 case REV_FOUNDATION_FVP_v9_6: 301 break; 302 default: 303 WARN("Unrecognized Foundation FVP revision %x\n", rev); 304 break; 305 } 306 break; 307 case HBI_BASE_FVP: 308 arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC); 309 310 /* 311 * Check for supported revisions 312 * Allow future revisions to run but emit warning diagnostic 313 */ 314 switch (rev) { 315 case REV_BASE_FVP_V0: 316 arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400; 317 break; 318 case REV_BASE_FVP_REVC: 319 arm_config.flags |= (ARM_CONFIG_FVP_HAS_SMMUV3 | 320 ARM_CONFIG_FVP_HAS_CCI5XX); 321 break; 322 default: 323 WARN("Unrecognized Base FVP revision %x\n", rev); 324 break; 325 } 326 break; 327 default: 328 ERROR("Unsupported board HBI number 0x%x\n", hbi); 329 panic(); 330 } 331 332 /* 333 * We assume that the presence of MT bit, and therefore shifted 334 * affinities, is uniform across the platform: either all CPUs, or no 335 * CPUs implement it. 336 */ 337 if ((read_mpidr_el1() & MPIDR_MT_MASK) != 0U) 338 arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF; 339 } 340 341 342 void __init fvp_interconnect_init(void) 343 { 344 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 345 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) { 346 ERROR("Unrecognized CCN variant detected. Only CCN-502 is supported"); 347 panic(); 348 } 349 350 plat_arm_interconnect_init(); 351 #else 352 uintptr_t cci_base = 0U; 353 const int *cci_map = NULL; 354 unsigned int map_size = 0U; 355 356 /* Initialize the right interconnect */ 357 if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) != 0U) { 358 cci_base = PLAT_FVP_CCI5XX_BASE; 359 cci_map = fvp_cci5xx_map; 360 map_size = ARRAY_SIZE(fvp_cci5xx_map); 361 } else if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) != 0U) { 362 cci_base = PLAT_FVP_CCI400_BASE; 363 cci_map = fvp_cci400_map; 364 map_size = ARRAY_SIZE(fvp_cci400_map); 365 } else { 366 return; 367 } 368 369 assert(cci_base != 0U); 370 assert(cci_map != NULL); 371 cci_init(cci_base, cci_map, map_size); 372 #endif 373 } 374 375 void fvp_interconnect_enable(void) 376 { 377 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 378 plat_arm_interconnect_enter_coherency(); 379 #else 380 unsigned int master; 381 382 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 383 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) { 384 master = get_interconnect_master(); 385 cci_enable_snoop_dvm_reqs(master); 386 } 387 #endif 388 } 389 390 void fvp_interconnect_disable(void) 391 { 392 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 393 plat_arm_interconnect_exit_coherency(); 394 #else 395 unsigned int master; 396 397 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 398 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) { 399 master = get_interconnect_master(); 400 cci_disable_snoop_dvm_reqs(master); 401 } 402 #endif 403 } 404 405 #if TRUSTED_BOARD_BOOT 406 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) 407 { 408 assert(heap_addr != NULL); 409 assert(heap_size != NULL); 410 411 return arm_get_mbedtls_heap(heap_addr, heap_size); 412 } 413 #endif 414