1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <stddef.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <bl31/bl31.h> 17 #include <common/bl_common.h> 18 #include <common/debug.h> 19 #include <cortex_a53.h> 20 #include <cortex_a57.h> 21 #include <denver.h> 22 #include <drivers/console.h> 23 #include <lib/mmio.h> 24 #include <lib/utils.h> 25 #include <lib/utils_def.h> 26 #include <plat/common/platform.h> 27 28 #include <memctrl.h> 29 #include <tegra_def.h> 30 #include <tegra_private.h> 31 32 /* length of Trusty's input parameters (in bytes) */ 33 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 34 35 extern void memcpy16(void *dest, const void *src, unsigned int length); 36 37 /******************************************************************************* 38 * Declarations of linker defined symbols which will help us find the layout 39 * of trusted SRAM 40 ******************************************************************************/ 41 42 IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START); 43 IMPORT_SYM(unsigned long, __RW_END__, BL31_RW_END); 44 IMPORT_SYM(unsigned long, __RODATA_START__, BL31_RODATA_BASE); 45 IMPORT_SYM(unsigned long, __RODATA_END__, BL31_RODATA_END); 46 IMPORT_SYM(unsigned long, __TEXT_START__, TEXT_START); 47 IMPORT_SYM(unsigned long, __TEXT_END__, TEXT_END); 48 49 extern uint64_t tegra_bl31_phys_base; 50 extern uint64_t tegra_console_base; 51 52 53 static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info; 54 static plat_params_from_bl2_t plat_bl31_params_from_bl2 = { 55 .tzdram_size = (uint64_t)TZDRAM_SIZE 56 }; 57 static unsigned long bl32_mem_size; 58 static unsigned long bl32_boot_params; 59 60 /******************************************************************************* 61 * This variable holds the non-secure image entry address 62 ******************************************************************************/ 63 extern uint64_t ns_image_entrypoint; 64 65 /******************************************************************************* 66 * The following platform setup functions are weakly defined. They 67 * provide typical implementations that will be overridden by a SoC. 68 ******************************************************************************/ 69 #pragma weak plat_early_platform_setup 70 #pragma weak plat_get_bl31_params 71 #pragma weak plat_get_bl31_plat_params 72 73 void plat_early_platform_setup(void) 74 { 75 ; /* do nothing */ 76 } 77 78 struct tegra_bl31_params *plat_get_bl31_params(void) 79 { 80 return NULL; 81 } 82 83 plat_params_from_bl2_t *plat_get_bl31_plat_params(void) 84 { 85 return NULL; 86 } 87 88 /******************************************************************************* 89 * Return a pointer to the 'entry_point_info' structure of the next image for 90 * security state specified. BL33 corresponds to the non-secure image type 91 * while BL32 corresponds to the secure image type. 92 ******************************************************************************/ 93 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 94 { 95 if (type == NON_SECURE) 96 return &bl33_image_ep_info; 97 98 /* return BL32 entry point info if it is valid */ 99 if (type == SECURE && bl32_image_ep_info.pc) 100 return &bl32_image_ep_info; 101 102 return NULL; 103 } 104 105 /******************************************************************************* 106 * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image 107 * passes this platform specific information. 108 ******************************************************************************/ 109 plat_params_from_bl2_t *bl31_get_plat_params(void) 110 { 111 return &plat_bl31_params_from_bl2; 112 } 113 114 /******************************************************************************* 115 * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image 116 * info. 117 ******************************************************************************/ 118 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 119 u_register_t arg2, u_register_t arg3) 120 { 121 struct tegra_bl31_params *arg_from_bl2 = (struct tegra_bl31_params *) arg0; 122 plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1; 123 image_info_t bl32_img_info = { {0} }; 124 uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end; 125 126 /* 127 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so 128 * there's no argument to relay from a previous bootloader. Platforms 129 * might use custom ways to get arguments, so provide handlers which 130 * they can override. 131 */ 132 if (arg_from_bl2 == NULL) 133 arg_from_bl2 = plat_get_bl31_params(); 134 if (plat_params == NULL) 135 plat_params = plat_get_bl31_plat_params(); 136 137 /* 138 * Copy BL3-3, BL3-2 entry point information. 139 * They are stored in Secure RAM, in BL2's address space. 140 */ 141 assert(arg_from_bl2); 142 assert(arg_from_bl2->bl33_ep_info); 143 bl33_image_ep_info = *arg_from_bl2->bl33_ep_info; 144 145 if (arg_from_bl2->bl32_ep_info) { 146 bl32_image_ep_info = *arg_from_bl2->bl32_ep_info; 147 bl32_mem_size = arg_from_bl2->bl32_ep_info->args.arg0; 148 bl32_boot_params = arg_from_bl2->bl32_ep_info->args.arg2; 149 } 150 151 /* 152 * Parse platform specific parameters - TZDRAM aperture base and size 153 */ 154 assert(plat_params); 155 plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base; 156 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size; 157 plat_bl31_params_from_bl2.uart_id = plat_params->uart_id; 158 159 /* 160 * It is very important that we run either from TZDRAM or TZSRAM base. 161 * Add an explicit check here. 162 */ 163 if ((plat_bl31_params_from_bl2.tzdram_base != BL31_BASE) && 164 (TEGRA_TZRAM_BASE != BL31_BASE)) 165 panic(); 166 167 /* 168 * Get the base address of the UART controller to be used for the 169 * console 170 */ 171 tegra_console_base = plat_get_console_from_id(plat_params->uart_id); 172 173 if (tegra_console_base != (uint64_t)0) { 174 /* 175 * Configure the UART port to be used as the console 176 */ 177 console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ, 178 TEGRA_CONSOLE_BAUDRATE); 179 } 180 181 /* 182 * Initialize delay timer 183 */ 184 tegra_delay_timer_init(); 185 186 /* 187 * Do initial security configuration to allow DRAM/device access. 188 */ 189 tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base, 190 plat_bl31_params_from_bl2.tzdram_size); 191 192 /* 193 * The previous bootloader might not have placed the BL32 image 194 * inside the TZDRAM. We check the BL32 image info to find out 195 * the base/PC values and relocate the image if necessary. 196 */ 197 if (arg_from_bl2->bl32_image_info) { 198 199 bl32_img_info = *arg_from_bl2->bl32_image_info; 200 201 /* Relocate BL32 if it resides outside of the TZDRAM */ 202 tzdram_start = plat_bl31_params_from_bl2.tzdram_base; 203 tzdram_end = plat_bl31_params_from_bl2.tzdram_base + 204 plat_bl31_params_from_bl2.tzdram_size; 205 bl32_start = bl32_img_info.image_base; 206 bl32_end = bl32_img_info.image_base + bl32_img_info.image_size; 207 208 assert(tzdram_end > tzdram_start); 209 assert(bl32_end > bl32_start); 210 assert(bl32_image_ep_info.pc > tzdram_start); 211 assert(bl32_image_ep_info.pc < tzdram_end); 212 213 /* relocate BL32 */ 214 if (bl32_start >= tzdram_end || bl32_end <= tzdram_start) { 215 216 INFO("Relocate BL32 to TZDRAM\n"); 217 218 memcpy16((void *)(uintptr_t)bl32_image_ep_info.pc, 219 (void *)(uintptr_t)bl32_start, 220 bl32_img_info.image_size); 221 222 /* clean up non-secure intermediate buffer */ 223 zeromem((void *)(uintptr_t)bl32_start, 224 bl32_img_info.image_size); 225 } 226 } 227 228 /* Early platform setup for Tegra SoCs */ 229 plat_early_platform_setup(); 230 231 INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", 232 (((read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK) 233 == DENVER_IMPL) ? "Denver" : "ARM", read_mpidr()); 234 } 235 236 #ifdef SPD_trusty 237 void plat_trusty_set_boot_args(aapcs64_params_t *args) 238 { 239 args->arg0 = bl32_mem_size; 240 args->arg1 = bl32_boot_params; 241 args->arg2 = TRUSTY_PARAMS_LEN_BYTES; 242 } 243 #endif 244 245 /******************************************************************************* 246 * Initialize the gic, configure the SCR. 247 ******************************************************************************/ 248 void bl31_platform_setup(void) 249 { 250 uint32_t tmp_reg; 251 252 /* Initialize the gic cpu and distributor interfaces */ 253 plat_gic_setup(); 254 255 /* 256 * Setup secondary CPU POR infrastructure. 257 */ 258 plat_secondary_setup(); 259 260 /* 261 * Initial Memory Controller configuration. 262 */ 263 tegra_memctrl_setup(); 264 265 /* 266 * Set up the TZRAM memory aperture to allow only secure world 267 * access 268 */ 269 tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE); 270 271 /* Set the next EL to be AArch64 */ 272 tmp_reg = SCR_RES1_BITS | SCR_RW_BIT; 273 write_scr(tmp_reg); 274 275 INFO("BL3-1: Tegra platform setup complete\n"); 276 } 277 278 /******************************************************************************* 279 * Perform any BL3-1 platform runtime setup prior to BL3-1 cold boot exit 280 ******************************************************************************/ 281 void bl31_plat_runtime_setup(void) 282 { 283 /* 284 * During boot, USB3 and flash media (SDMMC/SATA) devices need 285 * access to IRAM. Because these clients connect to the MC and 286 * do not have a direct path to the IRAM, the MC implements AHB 287 * redirection during boot to allow path to IRAM. In this mode 288 * accesses to a programmed memory address aperture are directed 289 * to the AHB bus, allowing access to the IRAM. This mode must be 290 * disabled before we jump to the non-secure world. 291 */ 292 tegra_memctrl_disable_ahb_redirection(); 293 } 294 295 /******************************************************************************* 296 * Perform the very early platform specific architectural setup here. At the 297 * moment this only intializes the mmu in a quick and dirty way. 298 ******************************************************************************/ 299 void bl31_plat_arch_setup(void) 300 { 301 unsigned long rw_start = BL31_RW_START; 302 unsigned long rw_size = BL31_RW_END - BL31_RW_START; 303 unsigned long rodata_start = BL31_RODATA_BASE; 304 unsigned long rodata_size = BL31_RODATA_END - BL31_RODATA_BASE; 305 unsigned long code_base = TEXT_START; 306 unsigned long code_size = TEXT_END - TEXT_START; 307 const mmap_region_t *plat_mmio_map = NULL; 308 #if USE_COHERENT_MEM 309 unsigned long coh_start, coh_size; 310 #endif 311 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 312 313 /* add memory regions */ 314 mmap_add_region(rw_start, rw_start, 315 rw_size, 316 MT_MEMORY | MT_RW | MT_SECURE); 317 mmap_add_region(rodata_start, rodata_start, 318 rodata_size, 319 MT_RO_DATA | MT_SECURE); 320 mmap_add_region(code_base, code_base, 321 code_size, 322 MT_CODE | MT_SECURE); 323 324 /* map TZDRAM used by BL31 as coherent memory */ 325 if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) { 326 mmap_add_region(params_from_bl2->tzdram_base, 327 params_from_bl2->tzdram_base, 328 BL31_SIZE, 329 MT_DEVICE | MT_RW | MT_SECURE); 330 } 331 332 #if USE_COHERENT_MEM 333 coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE); 334 coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE; 335 336 mmap_add_region(coh_start, coh_start, 337 coh_size, 338 MT_DEVICE | MT_RW | MT_SECURE); 339 #endif 340 341 /* map on-chip free running uS timer */ 342 mmap_add_region(page_align((uint64_t)TEGRA_TMRUS_BASE, 0), 343 page_align((uint64_t)TEGRA_TMRUS_BASE, 0), 344 (uint64_t)TEGRA_TMRUS_SIZE, 345 MT_DEVICE | MT_RO | MT_SECURE); 346 347 /* add MMIO space */ 348 plat_mmio_map = plat_get_mmio_map(); 349 if (plat_mmio_map) 350 mmap_add(plat_mmio_map); 351 else 352 WARN("MMIO map not available\n"); 353 354 /* set up translation tables */ 355 init_xlat_tables(); 356 357 /* enable the MMU */ 358 enable_mmu_el3(0); 359 360 INFO("BL3-1: Tegra: MMU enabled\n"); 361 } 362 363 /******************************************************************************* 364 * Check if the given NS DRAM range is valid 365 ******************************************************************************/ 366 int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes) 367 { 368 uint64_t end = base + size_in_bytes; 369 370 /* 371 * Check if the NS DRAM address is valid 372 */ 373 if ((base < TEGRA_DRAM_BASE) || (end > TEGRA_DRAM_END)) { 374 ERROR("NS address is out-of-bounds!\n"); 375 return -EFAULT; 376 } 377 378 /* 379 * TZDRAM aperture contains the BL31 and BL32 images, so we need 380 * to check if the NS DRAM range overlaps the TZDRAM aperture. 381 */ 382 if ((base < TZDRAM_END) && (end > tegra_bl31_phys_base)) { 383 ERROR("NS address overlaps TZDRAM!\n"); 384 return -ENOTSUP; 385 } 386 387 /* valid NS address */ 388 return 0; 389 } 390