1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <common/runtime_svc.h> 15 #include <lib/mmio.h> 16 17 #include <memctrl.h> 18 #include <tegra_platform.h> 19 #include <tegra_private.h> 20 21 /******************************************************************************* 22 * Common Tegra SiP SMCs 23 ******************************************************************************/ 24 #define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003 25 #define TEGRA_SIP_FIQ_NS_ENTRYPOINT 0x82000005 26 #define TEGRA_SIP_FIQ_NS_GET_CONTEXT 0x82000006 27 #define TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND 0xC2000007 28 29 /******************************************************************************* 30 * Fake system suspend mode control var 31 ******************************************************************************/ 32 extern uint8_t tegra_fake_system_suspend; 33 34 35 /******************************************************************************* 36 * SoC specific SiP handler 37 ******************************************************************************/ 38 #pragma weak plat_sip_handler 39 int plat_sip_handler(uint32_t smc_fid, 40 uint64_t x1, 41 uint64_t x2, 42 uint64_t x3, 43 uint64_t x4, 44 void *cookie, 45 void *handle, 46 uint64_t flags) 47 { 48 return -ENOTSUP; 49 } 50 51 /******************************************************************************* 52 * This function is responsible for handling all SiP calls 53 ******************************************************************************/ 54 uintptr_t tegra_sip_handler(uint32_t smc_fid, 55 u_register_t x1, 56 u_register_t x2, 57 u_register_t x3, 58 u_register_t x4, 59 void *cookie, 60 void *handle, 61 u_register_t flags) 62 { 63 uint32_t regval; 64 int err; 65 66 /* Check if this is a SoC specific SiP */ 67 err = plat_sip_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); 68 if (err == 0) 69 SMC_RET1(handle, (uint64_t)err); 70 71 switch (smc_fid) { 72 73 case TEGRA_SIP_NEW_VIDEOMEM_REGION: 74 75 /* clean up the high bits */ 76 x2 = (uint32_t)x2; 77 78 /* 79 * Check if Video Memory overlaps TZDRAM (contains bl31/bl32) 80 * or falls outside of the valid DRAM range 81 */ 82 err = bl31_check_ns_address(x1, x2); 83 if (err) 84 SMC_RET1(handle, err); 85 86 /* 87 * Check if Video Memory is aligned to 1MB. 88 */ 89 if ((x1 & 0xFFFFF) || (x2 & 0xFFFFF)) { 90 ERROR("Unaligned Video Memory base address!\n"); 91 SMC_RET1(handle, -ENOTSUP); 92 } 93 94 /* 95 * The GPU is the user of the Video Memory region. In order to 96 * transition to the new memory region smoothly, we program the 97 * new base/size ONLY if the GPU is in reset mode. 98 */ 99 regval = mmio_read_32(TEGRA_CAR_RESET_BASE + 100 TEGRA_GPU_RESET_REG_OFFSET); 101 if ((regval & GPU_RESET_BIT) == 0U) { 102 ERROR("GPU not in reset! Video Memory setup failed\n"); 103 SMC_RET1(handle, -ENOTSUP); 104 } 105 106 /* new video memory carveout settings */ 107 tegra_memctrl_videomem_setup(x1, x2); 108 109 SMC_RET1(handle, 0); 110 break; 111 112 /* 113 * The NS world registers the address of its handler to be 114 * used for processing the FIQ. This is normally used by the 115 * NS FIQ debugger driver to detect system hangs by programming 116 * a watchdog timer to fire a FIQ interrupt. 117 */ 118 case TEGRA_SIP_FIQ_NS_ENTRYPOINT: 119 120 if (!x1) 121 SMC_RET1(handle, SMC_UNK); 122 123 /* 124 * TODO: Check if x1 contains a valid DRAM address 125 */ 126 127 /* store the NS world's entrypoint */ 128 tegra_fiq_set_ns_entrypoint(x1); 129 130 SMC_RET1(handle, 0); 131 break; 132 133 /* 134 * The NS world's FIQ handler issues this SMC to get the NS EL1/EL0 135 * CPU context when the FIQ interrupt was triggered. This allows the 136 * NS world to understand the CPU state when the watchdog interrupt 137 * triggered. 138 */ 139 case TEGRA_SIP_FIQ_NS_GET_CONTEXT: 140 141 /* retrieve context registers when FIQ triggered */ 142 tegra_fiq_get_intr_context(); 143 144 SMC_RET0(handle); 145 break; 146 147 case TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND: 148 /* 149 * System suspend fake mode is set if we are on VDK and we make 150 * a debug SIP call. This mode ensures that we excercise debug 151 * path instead of the regular code path to suit the pre-silicon 152 * platform needs. These include replacing the call to WFI by 153 * a warm reset request. 154 */ 155 if (tegra_platform_is_emulation() != 0U) { 156 157 tegra_fake_system_suspend = 1; 158 SMC_RET1(handle, 0); 159 } 160 161 /* 162 * We return to the external world as if this SIP is not 163 * implemented in case, we are not running on VDK. 164 */ 165 break; 166 167 default: 168 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 169 break; 170 } 171 172 SMC_RET1(handle, SMC_UNK); 173 } 174 175 /* Define a runtime service descriptor for fast SMC calls */ 176 DECLARE_RT_SVC( 177 tegra_sip_fast, 178 179 OEN_SIP_START, 180 OEN_SIP_END, 181 SMC_TYPE_FAST, 182 NULL, 183 tegra_sip_handler 184 ); 185