1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef TEGRA_PRIVATE_H 8 #define TEGRA_PRIVATE_H 9 10 #include <platform_def.h> 11 12 #include <arch.h> 13 #include <arch_helpers.h> 14 #include <lib/psci/psci.h> 15 #include <lib/xlat_tables/xlat_tables_v2.h> 16 17 #include <tegra_gic.h> 18 19 /******************************************************************************* 20 * Tegra DRAM memory base address 21 ******************************************************************************/ 22 #define TEGRA_DRAM_BASE ULL(0x80000000) 23 #define TEGRA_DRAM_END ULL(0x27FFFFFFF) 24 25 /******************************************************************************* 26 * Struct for parameters received from BL2 27 ******************************************************************************/ 28 typedef struct plat_params_from_bl2 { 29 /* TZ memory size */ 30 uint64_t tzdram_size; 31 /* TZ memory base */ 32 uint64_t tzdram_base; 33 /* UART port ID */ 34 int uart_id; 35 } plat_params_from_bl2_t; 36 37 /******************************************************************************* 38 * Struct describing parameters passed to bl31 39 ******************************************************************************/ 40 struct tegra_bl31_params { 41 param_header_t h; 42 image_info_t *bl31_image_info; 43 entry_point_info_t *bl32_ep_info; 44 image_info_t *bl32_image_info; 45 entry_point_info_t *bl33_ep_info; 46 image_info_t *bl33_image_info; 47 }; 48 49 /* Declarations for plat_psci_handlers.c */ 50 int32_t tegra_soc_validate_power_state(unsigned int power_state, 51 psci_power_state_t *req_state); 52 53 /* Declarations for plat_setup.c */ 54 const mmap_region_t *plat_get_mmio_map(void); 55 uint32_t plat_get_console_from_id(int id); 56 void plat_gic_setup(void); 57 struct tegra_bl31_params *plat_get_bl31_params(void); 58 plat_params_from_bl2_t *plat_get_bl31_plat_params(void); 59 60 /* Declarations for plat_secondary.c */ 61 void plat_secondary_setup(void); 62 int plat_lock_cpu_vectors(void); 63 64 /* Declarations for tegra_fiq_glue.c */ 65 void tegra_fiq_handler_setup(void); 66 int tegra_fiq_get_intr_context(void); 67 void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint); 68 69 /* Declarations for tegra_security.c */ 70 void tegra_security_setup(void); 71 void tegra_security_setup_videomem(uintptr_t base, uint64_t size); 72 73 /* Declarations for tegra_pm.c */ 74 extern uint8_t tegra_fake_system_suspend; 75 76 void tegra_pm_system_suspend_entry(void); 77 void tegra_pm_system_suspend_exit(void); 78 int tegra_system_suspended(void); 79 80 /* Declarations for tegraXXX_pm.c */ 81 int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl); 82 int tegra_prepare_cpu_on_finish(unsigned long mpidr); 83 84 /* Declarations for tegra_bl31_setup.c */ 85 plat_params_from_bl2_t *bl31_get_plat_params(void); 86 int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes); 87 void plat_early_platform_setup(void); 88 89 /* Declarations for tegra_delay_timer.c */ 90 void tegra_delay_timer_init(void); 91 92 void tegra_secure_entrypoint(void); 93 void tegra186_cpu_reset_handler(void); 94 95 #endif /* TEGRA_PRIVATE_H */ 96