1 /* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <drivers/arm/gicv3.h> 13 #include <lib/extensions/spe.h> 14 #include <lib/mmio.h> 15 #include <lib/psci/psci.h> 16 #include <plat/common/platform.h> 17 18 #include <arm_config.h> 19 #include <plat_arm.h> 20 #include <v2m_def.h> 21 22 #include "../../../../drivers/arm/gic/v3/gicv3_private.h" 23 #include "drivers/pwrc/fvp_pwrc.h" 24 #include "fvp_def.h" 25 #include "fvp_private.h" 26 27 28 #if ARM_RECOM_STATE_ID_ENC 29 /* 30 * The table storing the valid idle power states. Ensure that the 31 * array entries are populated in ascending order of state-id to 32 * enable us to use binary search during power state validation. 33 * The table must be terminated by a NULL entry. 34 */ 35 const unsigned int arm_pm_idle_states[] = { 36 /* State-id - 0x01 */ 37 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RET, 38 ARM_PWR_LVL0, PSTATE_TYPE_STANDBY), 39 /* State-id - 0x02 */ 40 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF, 41 ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN), 42 /* State-id - 0x22 */ 43 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF, 44 ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN), 45 /* State-id - 0x222 */ 46 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF, 47 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL2, PSTATE_TYPE_POWERDOWN), 48 0, 49 }; 50 #endif 51 52 /******************************************************************************* 53 * Function which implements the common FVP specific operations to power down a 54 * cluster in response to a CPU_OFF or CPU_SUSPEND request. 55 ******************************************************************************/ 56 static void fvp_cluster_pwrdwn_common(void) 57 { 58 uint64_t mpidr = read_mpidr_el1(); 59 60 #if ENABLE_SPE_FOR_LOWER_ELS 61 /* 62 * On power down we need to disable statistical profiling extensions 63 * before exiting coherency. 64 */ 65 spe_disable(); 66 #endif 67 68 /* Disable coherency if this cluster is to be turned off */ 69 fvp_interconnect_disable(); 70 71 /* Program the power controller to turn the cluster off */ 72 fvp_pwrc_write_pcoffr(mpidr); 73 } 74 75 /* 76 * Empty implementation of these hooks avoid setting the GICR_WAKER.Sleep bit 77 * on ARM GICv3 implementations on FVP. This is required, because FVP does not 78 * support SYSTEM_SUSPEND and it is `faked` in firmware. Hence, for wake up 79 * from `fake` system suspend the GIC must not be powered off. 80 */ 81 void arm_gicv3_distif_pre_save(unsigned int rdist_proc_num) 82 {} 83 84 void arm_gicv3_distif_post_restore(unsigned int rdist_proc_num) 85 {} 86 87 static void fvp_power_domain_on_finish_common(const psci_power_state_t *target_state) 88 { 89 unsigned long mpidr; 90 91 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 92 ARM_LOCAL_STATE_OFF); 93 94 /* Get the mpidr for this cpu */ 95 mpidr = read_mpidr_el1(); 96 97 /* Perform the common cluster specific operations */ 98 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 99 ARM_LOCAL_STATE_OFF) { 100 /* 101 * This CPU might have woken up whilst the cluster was 102 * attempting to power down. In this case the FVP power 103 * controller will have a pending cluster power off request 104 * which needs to be cleared by writing to the PPONR register. 105 * This prevents the power controller from interpreting a 106 * subsequent entry of this cpu into a simple wfi as a power 107 * down request. 108 */ 109 fvp_pwrc_write_pponr(mpidr); 110 111 /* Enable coherency if this cluster was off */ 112 fvp_interconnect_enable(); 113 } 114 /* Perform the common system specific operations */ 115 if (target_state->pwr_domain_state[ARM_PWR_LVL2] == 116 ARM_LOCAL_STATE_OFF) 117 arm_system_pwr_domain_resume(); 118 119 /* 120 * Clear PWKUPR.WEN bit to ensure interrupts do not interfere 121 * with a cpu power down unless the bit is set again 122 */ 123 fvp_pwrc_clr_wen(mpidr); 124 } 125 126 127 /******************************************************************************* 128 * FVP handler called when a CPU is about to enter standby. 129 ******************************************************************************/ 130 static void fvp_cpu_standby(plat_local_state_t cpu_state) 131 { 132 133 assert(cpu_state == ARM_LOCAL_STATE_RET); 134 135 /* 136 * Enter standby state 137 * dsb is good practice before using wfi to enter low power states 138 */ 139 dsb(); 140 wfi(); 141 } 142 143 /******************************************************************************* 144 * FVP handler called when a power domain is about to be turned on. The 145 * mpidr determines the CPU to be turned on. 146 ******************************************************************************/ 147 static int fvp_pwr_domain_on(u_register_t mpidr) 148 { 149 int rc = PSCI_E_SUCCESS; 150 unsigned int psysr; 151 152 /* 153 * Ensure that we do not cancel an inflight power off request for the 154 * target cpu. That would leave it in a zombie wfi. Wait for it to power 155 * off and then program the power controller to turn that CPU on. 156 */ 157 do { 158 psysr = fvp_pwrc_read_psysr(mpidr); 159 } while ((psysr & PSYSR_AFF_L0) != 0U); 160 161 fvp_pwrc_write_pponr(mpidr); 162 return rc; 163 } 164 165 /******************************************************************************* 166 * FVP handler called when a power domain is about to be turned off. The 167 * target_state encodes the power state that each level should transition to. 168 ******************************************************************************/ 169 static void fvp_pwr_domain_off(const psci_power_state_t *target_state) 170 { 171 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 172 ARM_LOCAL_STATE_OFF); 173 174 /* 175 * If execution reaches this stage then this power domain will be 176 * suspended. Perform at least the cpu specific actions followed 177 * by the cluster specific operations if applicable. 178 */ 179 180 /* Prevent interrupts from spuriously waking up this cpu */ 181 plat_arm_gic_cpuif_disable(); 182 183 /* Turn redistributor off */ 184 plat_arm_gic_redistif_off(); 185 186 /* Program the power controller to power off this cpu. */ 187 fvp_pwrc_write_ppoffr(read_mpidr_el1()); 188 189 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 190 ARM_LOCAL_STATE_OFF) 191 fvp_cluster_pwrdwn_common(); 192 193 } 194 195 /******************************************************************************* 196 * FVP handler called when a power domain is about to be suspended. The 197 * target_state encodes the power state that each level should transition to. 198 ******************************************************************************/ 199 static void fvp_pwr_domain_suspend(const psci_power_state_t *target_state) 200 { 201 unsigned long mpidr; 202 203 /* 204 * FVP has retention only at cpu level. Just return 205 * as nothing is to be done for retention. 206 */ 207 if (target_state->pwr_domain_state[ARM_PWR_LVL0] == 208 ARM_LOCAL_STATE_RET) 209 return; 210 211 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 212 ARM_LOCAL_STATE_OFF); 213 214 /* Get the mpidr for this cpu */ 215 mpidr = read_mpidr_el1(); 216 217 /* Program the power controller to enable wakeup interrupts. */ 218 fvp_pwrc_set_wen(mpidr); 219 220 /* Prevent interrupts from spuriously waking up this cpu */ 221 plat_arm_gic_cpuif_disable(); 222 223 /* 224 * The Redistributor is not powered off as it can potentially prevent 225 * wake up events reaching the CPUIF and/or might lead to losing 226 * register context. 227 */ 228 229 /* Perform the common cluster specific operations */ 230 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 231 ARM_LOCAL_STATE_OFF) 232 fvp_cluster_pwrdwn_common(); 233 234 /* Perform the common system specific operations */ 235 if (target_state->pwr_domain_state[ARM_PWR_LVL2] == 236 ARM_LOCAL_STATE_OFF) 237 arm_system_pwr_domain_save(); 238 239 /* Program the power controller to power off this cpu. */ 240 fvp_pwrc_write_ppoffr(read_mpidr_el1()); 241 } 242 243 /******************************************************************************* 244 * FVP handler called when a power domain has just been powered on after 245 * being turned off earlier. The target_state encodes the low power state that 246 * each level has woken up from. 247 ******************************************************************************/ 248 static void fvp_pwr_domain_on_finish(const psci_power_state_t *target_state) 249 { 250 fvp_power_domain_on_finish_common(target_state); 251 252 /* Enable the gic cpu interface */ 253 plat_arm_gic_pcpu_init(); 254 255 /* Program the gic per-cpu distributor or re-distributor interface */ 256 plat_arm_gic_cpuif_enable(); 257 } 258 259 /******************************************************************************* 260 * FVP handler called when a power domain has just been powered on after 261 * having been suspended earlier. The target_state encodes the low power state 262 * that each level has woken up from. 263 * TODO: At the moment we reuse the on finisher and reinitialize the secure 264 * context. Need to implement a separate suspend finisher. 265 ******************************************************************************/ 266 static void fvp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) 267 { 268 /* 269 * Nothing to be done on waking up from retention from CPU level. 270 */ 271 if (target_state->pwr_domain_state[ARM_PWR_LVL0] == 272 ARM_LOCAL_STATE_RET) 273 return; 274 275 fvp_power_domain_on_finish_common(target_state); 276 277 /* Enable the gic cpu interface */ 278 plat_arm_gic_cpuif_enable(); 279 } 280 281 /******************************************************************************* 282 * FVP handlers to shutdown/reboot the system 283 ******************************************************************************/ 284 static void __dead2 fvp_system_off(void) 285 { 286 /* Write the System Configuration Control Register */ 287 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL, 288 V2M_CFGCTRL_START | 289 V2M_CFGCTRL_RW | 290 V2M_CFGCTRL_FUNC(V2M_FUNC_SHUTDOWN)); 291 wfi(); 292 ERROR("FVP System Off: operation not handled.\n"); 293 panic(); 294 } 295 296 static void __dead2 fvp_system_reset(void) 297 { 298 /* Write the System Configuration Control Register */ 299 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL, 300 V2M_CFGCTRL_START | 301 V2M_CFGCTRL_RW | 302 V2M_CFGCTRL_FUNC(V2M_FUNC_REBOOT)); 303 wfi(); 304 ERROR("FVP System Reset: operation not handled.\n"); 305 panic(); 306 } 307 308 static int fvp_node_hw_state(u_register_t target_cpu, 309 unsigned int power_level) 310 { 311 unsigned int psysr; 312 int ret; 313 314 /* 315 * The format of 'power_level' is implementation-defined, but 0 must 316 * mean a CPU. We also allow 1 to denote the cluster 317 */ 318 if ((power_level != ARM_PWR_LVL0) && (power_level != ARM_PWR_LVL1)) 319 return PSCI_E_INVALID_PARAMS; 320 321 /* 322 * Read the status of the given MPDIR from FVP power controller. The 323 * power controller only gives us on/off status, so map that to expected 324 * return values of the PSCI call 325 */ 326 psysr = fvp_pwrc_read_psysr(target_cpu); 327 if (psysr == PSYSR_INVALID) 328 return PSCI_E_INVALID_PARAMS; 329 330 if (power_level == ARM_PWR_LVL0) { 331 ret = ((psysr & PSYSR_AFF_L0) != 0U) ? HW_ON : HW_OFF; 332 } else { 333 /* power_level == ARM_PWR_LVL1 */ 334 ret = ((psysr & PSYSR_AFF_L1) != 0U) ? HW_ON : HW_OFF; 335 } 336 337 return ret; 338 } 339 340 /* 341 * The FVP doesn't truly support power management at SYSTEM power domain. The 342 * SYSTEM_SUSPEND will be down-graded to the cluster level within the platform 343 * layer. The `fake` SYSTEM_SUSPEND allows us to validate some of the driver 344 * save and restore sequences on FVP. 345 */ 346 #if !ARM_BL31_IN_DRAM 347 static void fvp_get_sys_suspend_power_state(psci_power_state_t *req_state) 348 { 349 unsigned int i; 350 351 for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++) 352 req_state->pwr_domain_state[i] = ARM_LOCAL_STATE_OFF; 353 } 354 #endif 355 356 /******************************************************************************* 357 * Handler to filter PSCI requests. 358 ******************************************************************************/ 359 /* 360 * The system power domain suspend is only supported only via 361 * PSCI SYSTEM_SUSPEND API. PSCI CPU_SUSPEND request to system power domain 362 * will be downgraded to the lower level. 363 */ 364 static int fvp_validate_power_state(unsigned int power_state, 365 psci_power_state_t *req_state) 366 { 367 int rc; 368 rc = arm_validate_power_state(power_state, req_state); 369 370 /* 371 * Ensure that the system power domain level is never suspended 372 * via PSCI CPU SUSPEND API. Currently system suspend is only 373 * supported via PSCI SYSTEM SUSPEND API. 374 */ 375 req_state->pwr_domain_state[ARM_PWR_LVL2] = ARM_LOCAL_STATE_RUN; 376 return rc; 377 } 378 379 /* 380 * Custom `translate_power_state_by_mpidr` handler for FVP. Unlike in the 381 * `fvp_validate_power_state`, we do not downgrade the system power 382 * domain level request in `power_state` as it will be used to query the 383 * PSCI_STAT_COUNT/RESIDENCY at the system power domain level. 384 */ 385 static int fvp_translate_power_state_by_mpidr(u_register_t mpidr, 386 unsigned int power_state, 387 psci_power_state_t *output_state) 388 { 389 return arm_validate_power_state(power_state, output_state); 390 } 391 392 /******************************************************************************* 393 * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard 394 * platform layer will take care of registering the handlers with PSCI. 395 ******************************************************************************/ 396 plat_psci_ops_t plat_arm_psci_pm_ops = { 397 .cpu_standby = fvp_cpu_standby, 398 .pwr_domain_on = fvp_pwr_domain_on, 399 .pwr_domain_off = fvp_pwr_domain_off, 400 .pwr_domain_suspend = fvp_pwr_domain_suspend, 401 .pwr_domain_on_finish = fvp_pwr_domain_on_finish, 402 .pwr_domain_suspend_finish = fvp_pwr_domain_suspend_finish, 403 .system_off = fvp_system_off, 404 .system_reset = fvp_system_reset, 405 .validate_power_state = fvp_validate_power_state, 406 .validate_ns_entrypoint = arm_validate_psci_entrypoint, 407 .translate_power_state_by_mpidr = fvp_translate_power_state_by_mpidr, 408 .get_node_hw_state = fvp_node_hw_state, 409 #if !ARM_BL31_IN_DRAM 410 /* 411 * The TrustZone Controller is set up during the warmboot sequence after 412 * resuming the CPU from a SYSTEM_SUSPEND. If BL31 is located in SRAM 413 * this is not a problem but, if it is in TZC-secured DRAM, it tries to 414 * reconfigure the same memory it is running on, causing an exception. 415 */ 416 .get_sys_suspend_power_state = fvp_get_sys_suspend_power_state, 417 #endif 418 .mem_protect_chk = arm_psci_mem_protect_chk, 419 .read_mem_protect = arm_psci_read_mem_protect, 420 .write_mem_protect = arm_nor_psci_write_mem_protect, 421 }; 422 423 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) 424 { 425 return ops; 426 } 427