1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018, Icenowy Zheng <icenowy@aosc.io> 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <allwinner/sunxi_rsb.h> 9 #include <arch_helpers.h> 10 #include <debug.h> 11 #include <delay_timer.h> 12 #include <errno.h> 13 #include <libfdt.h> 14 #include <mmio.h> 15 #include <platform_def.h> 16 #include <sunxi_def.h> 17 #include <sunxi_mmap.h> 18 #include <sunxi_private.h> 19 20 static enum pmic_type { 21 GENERIC_H5, 22 GENERIC_A64, 23 REF_DESIGN_H5, /* regulators controlled by GPIO pins on port L */ 24 AXP803_RSB, /* PMIC connected via RSB on most A64 boards */ 25 } pmic; 26 27 #define AXP803_HW_ADDR 0x3a3 28 #define AXP803_RT_ADDR 0x2d 29 30 /* 31 * On boards without a proper PMIC we struggle to turn off the system properly. 32 * Try to turn off as much off the system as we can, to reduce power 33 * consumption. This should be entered with only one core running and SMP 34 * disabled. 35 * This function only cares about peripherals. 36 */ 37 void sunxi_turn_off_soc(uint16_t socid) 38 { 39 int i; 40 41 /** Turn off most peripherals, most importantly DRAM users. **/ 42 /* Keep DRAM controller running for now. */ 43 mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c0, ~BIT_32(14)); 44 mmio_clrbits_32(SUNXI_CCU_BASE + 0x60, ~BIT_32(14)); 45 /* Contains msgbox (bit 21) and spinlock (bit 22) */ 46 mmio_write_32(SUNXI_CCU_BASE + 0x2c4, 0); 47 mmio_write_32(SUNXI_CCU_BASE + 0x64, 0); 48 mmio_write_32(SUNXI_CCU_BASE + 0x2c8, 0); 49 /* Keep PIO controller running for now. */ 50 mmio_clrbits_32(SUNXI_CCU_BASE + 0x68, ~(BIT_32(5))); 51 mmio_write_32(SUNXI_CCU_BASE + 0x2d0, 0); 52 /* Contains UART0 (bit 16) */ 53 mmio_write_32(SUNXI_CCU_BASE + 0x2d8, 0); 54 mmio_write_32(SUNXI_CCU_BASE + 0x6c, 0); 55 mmio_write_32(SUNXI_CCU_BASE + 0x70, 0); 56 57 /** Turn off DRAM controller. **/ 58 mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c0, BIT_32(14)); 59 mmio_clrbits_32(SUNXI_CCU_BASE + 0x60, BIT_32(14)); 60 61 /** Migrate CPU and bus clocks away from the PLLs. **/ 62 /* AHB1: use OSC24M/1, APB1 = AHB1 / 2 */ 63 mmio_write_32(SUNXI_CCU_BASE + 0x54, 0x1000); 64 /* APB2: use OSC24M */ 65 mmio_write_32(SUNXI_CCU_BASE + 0x58, 0x1000000); 66 /* AHB2: use AHB1 clock */ 67 mmio_write_32(SUNXI_CCU_BASE + 0x5c, 0); 68 /* CPU: use OSC24M */ 69 mmio_write_32(SUNXI_CCU_BASE + 0x50, 0x10000); 70 71 /** Turn off PLLs. **/ 72 for (i = 0; i < 6; i++) 73 mmio_clrbits_32(SUNXI_CCU_BASE + i * 8, BIT(31)); 74 switch (socid) { 75 case SUNXI_SOC_H5: 76 mmio_clrbits_32(SUNXI_CCU_BASE + 0x44, BIT(31)); 77 break; 78 case SUNXI_SOC_A64: 79 mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c, BIT(31)); 80 mmio_clrbits_32(SUNXI_CCU_BASE + 0x4c, BIT(31)); 81 break; 82 } 83 } 84 85 static int rsb_init(void) 86 { 87 int ret; 88 89 ret = rsb_init_controller(); 90 if (ret) 91 return ret; 92 93 /* Start with 400 KHz to issue the I2C->RSB switch command. */ 94 ret = rsb_set_bus_speed(SUNXI_OSC24M_CLK_IN_HZ, 400000); 95 if (ret) 96 return ret; 97 98 /* 99 * Initiate an I2C transaction to write 0x7c into register 0x3e, 100 * switching the PMIC to RSB mode. 101 */ 102 ret = rsb_set_device_mode(0x7c3e00); 103 if (ret) 104 return ret; 105 106 /* Now in RSB mode, switch to the recommended 3 MHz. */ 107 ret = rsb_set_bus_speed(SUNXI_OSC24M_CLK_IN_HZ, 3000000); 108 if (ret) 109 return ret; 110 111 /* Associate the 8-bit runtime address with the 12-bit bus address. */ 112 return rsb_assign_runtime_address(AXP803_HW_ADDR, 113 AXP803_RT_ADDR); 114 } 115 116 static int axp_write(uint8_t reg, uint8_t val) 117 { 118 return rsb_write(AXP803_RT_ADDR, reg, val); 119 } 120 121 static int axp_setbits(uint8_t reg, uint8_t set_mask) 122 { 123 uint8_t regval; 124 int ret; 125 126 ret = rsb_read(AXP803_RT_ADDR, reg); 127 if (ret < 0) 128 return ret; 129 130 regval = ret | set_mask; 131 132 return rsb_write(AXP803_RT_ADDR, reg, regval); 133 } 134 135 static bool should_enable_regulator(const void *fdt, int node) 136 { 137 if (fdt_getprop(fdt, node, "phandle", NULL) != NULL) 138 return true; 139 if (fdt_getprop(fdt, node, "regulator-always-on", NULL) != NULL) 140 return true; 141 return false; 142 } 143 144 /* 145 * Retrieve the voltage from a given regulator DTB node. 146 * Both the regulator-{min,max}-microvolt properties must be present and 147 * have the same value. Return that value in millivolts. 148 */ 149 static int fdt_get_regulator_millivolt(const void *fdt, int node) 150 { 151 const fdt32_t *prop; 152 uint32_t min_volt; 153 154 prop = fdt_getprop(fdt, node, "regulator-min-microvolt", NULL); 155 if (prop == NULL) 156 return -EINVAL; 157 min_volt = fdt32_to_cpu(*prop); 158 159 prop = fdt_getprop(fdt, node, "regulator-max-microvolt", NULL); 160 if (prop == NULL) 161 return -EINVAL; 162 163 if (fdt32_to_cpu(*prop) != min_volt) 164 return -EINVAL; 165 166 return min_volt / 1000; 167 } 168 169 #define NO_SPLIT 0xff 170 171 struct axp_regulator { 172 char *dt_name; 173 uint16_t min_volt; 174 uint16_t max_volt; 175 uint16_t step; 176 unsigned char split; 177 unsigned char volt_reg; 178 unsigned char switch_reg; 179 unsigned char switch_bit; 180 } regulators[] = { 181 {"dcdc1", 1600, 3400, 100, NO_SPLIT, 0x20, 0xff, 9}, 182 {"dcdc5", 800, 1840, 10, 32, 0x24, 0xff, 9}, 183 {"dldo1", 700, 3300, 100, NO_SPLIT, 0x15, 0x12, 3}, 184 {"dldo2", 700, 4200, 100, 27, 0x16, 0x12, 4}, 185 {"dldo3", 700, 3300, 100, NO_SPLIT, 0x17, 0x12, 5}, 186 {"fldo1", 700, 1450, 50, NO_SPLIT, 0x1c, 0x13, 2}, 187 {} 188 }; 189 190 static int setup_regulator(const void *fdt, int node, 191 const struct axp_regulator *reg) 192 { 193 int mvolt; 194 uint8_t regval; 195 196 if (!should_enable_regulator(fdt, node)) 197 return -ENOENT; 198 199 mvolt = fdt_get_regulator_millivolt(fdt, node); 200 if (mvolt < reg->min_volt || mvolt > reg->max_volt) 201 return -EINVAL; 202 203 regval = (mvolt / reg->step) - (reg->min_volt / reg->step); 204 if (regval > reg->split) 205 regval = ((regval - reg->split) / 2) + reg->split; 206 207 axp_write(reg->volt_reg, regval); 208 if (reg->switch_reg < 0xff) 209 axp_setbits(reg->switch_reg, BIT(reg->switch_bit)); 210 211 INFO("PMIC: AXP803: %s voltage: %d.%03dV\n", reg->dt_name, 212 mvolt / 1000, mvolt % 1000); 213 214 return 0; 215 } 216 217 static void setup_axp803_rails(const void *fdt) 218 { 219 int node; 220 bool dc1sw = false; 221 222 /* locate the PMIC DT node, bail out if not found */ 223 node = fdt_node_offset_by_compatible(fdt, -1, "x-powers,axp803"); 224 if (node == -FDT_ERR_NOTFOUND) { 225 WARN("BL31: PMIC: No AXP803 DT node, skipping initial setup.\n"); 226 return; 227 } 228 229 if (fdt_getprop(fdt, node, "x-powers,drive-vbus-en", NULL)) 230 axp_setbits(0x8f, BIT(4)); 231 232 /* descend into the "regulators" subnode */ 233 node = fdt_first_subnode(fdt, node); 234 235 /* iterate over all regulators to find used ones */ 236 for (node = fdt_first_subnode(fdt, node); 237 node != -FDT_ERR_NOTFOUND; 238 node = fdt_next_subnode(fdt, node)) { 239 struct axp_regulator *reg; 240 const char *name; 241 int length; 242 243 /* We only care if it's always on or referenced. */ 244 if (!should_enable_regulator(fdt, node)) 245 continue; 246 247 name = fdt_get_name(fdt, node, &length); 248 for (reg = regulators; reg->dt_name; reg++) { 249 if (!strncmp(name, reg->dt_name, length)) { 250 setup_regulator(fdt, node, reg); 251 break; 252 } 253 } 254 255 if (!strncmp(name, "dc1sw", length)) { 256 /* Delay DC1SW enablement to avoid overheating. */ 257 dc1sw = true; 258 continue; 259 } 260 } 261 /* 262 * If DLDO2 is enabled after DC1SW, the PMIC overheats and shuts 263 * down. So always enable DC1SW as the very last regulator. 264 */ 265 if (dc1sw) { 266 INFO("PMIC: AXP803: Enabling DC1SW\n"); 267 axp_setbits(0x12, BIT(7)); 268 } 269 } 270 271 int sunxi_pmic_setup(uint16_t socid, const void *fdt) 272 { 273 int ret; 274 275 switch (socid) { 276 case SUNXI_SOC_H5: 277 pmic = REF_DESIGN_H5; 278 NOTICE("BL31: PMIC: Defaulting to PortL GPIO according to H5 reference design.\n"); 279 break; 280 case SUNXI_SOC_A64: 281 pmic = GENERIC_A64; 282 ret = sunxi_init_platform_r_twi(socid, true); 283 if (ret) 284 return ret; 285 286 ret = rsb_init(); 287 if (ret) 288 return ret; 289 290 pmic = AXP803_RSB; 291 NOTICE("BL31: PMIC: Detected AXP803 on RSB.\n"); 292 293 if (fdt) 294 setup_axp803_rails(fdt); 295 296 break; 297 default: 298 NOTICE("BL31: PMIC: No support for Allwinner %x SoC.\n", socid); 299 return -ENODEV; 300 } 301 return 0; 302 } 303 304 void __dead2 sunxi_power_down(void) 305 { 306 switch (pmic) { 307 case GENERIC_H5: 308 /* Turn off as many peripherals and clocks as we can. */ 309 sunxi_turn_off_soc(SUNXI_SOC_H5); 310 /* Turn off the pin controller now. */ 311 mmio_write_32(SUNXI_CCU_BASE + 0x68, 0); 312 break; 313 case GENERIC_A64: 314 /* Turn off as many peripherals and clocks as we can. */ 315 sunxi_turn_off_soc(SUNXI_SOC_A64); 316 /* Turn off the pin controller now. */ 317 mmio_write_32(SUNXI_CCU_BASE + 0x68, 0); 318 break; 319 case REF_DESIGN_H5: 320 sunxi_turn_off_soc(SUNXI_SOC_H5); 321 322 /* 323 * Switch PL pins to power off the board: 324 * - PL5 (VCC_IO) -> high 325 * - PL8 (PWR-STB = CPU power supply) -> low 326 * - PL9 (PWR-DRAM) ->low 327 * - PL10 (power LED) -> low 328 * Note: Clearing PL8 will reset the board, so keep it up. 329 */ 330 sunxi_set_gpio_out('L', 5, 1); 331 sunxi_set_gpio_out('L', 9, 0); 332 sunxi_set_gpio_out('L', 10, 0); 333 334 /* Turn off pin controller now. */ 335 mmio_write_32(SUNXI_CCU_BASE + 0x68, 0); 336 337 break; 338 case AXP803_RSB: 339 /* (Re-)init RSB in case the rich OS has disabled it. */ 340 sunxi_init_platform_r_twi(SUNXI_SOC_A64, true); 341 rsb_init(); 342 343 /* Set "power disable control" bit */ 344 axp_setbits(0x32, BIT(7)); 345 break; 346 default: 347 break; 348 } 349 350 udelay(1000); 351 ERROR("PSCI: Cannot turn off system, halting.\n"); 352 wfi(); 353 panic(); 354 } 355