1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <context.h> 15 #include <drivers/console.h> 16 #include <lib/el3_runtime/context_mgmt.h> 17 #include <lib/mmio.h> 18 #include <lib/psci/psci.h> 19 #include <plat/common/platform.h> 20 21 #include <memctrl.h> 22 #include <pmc.h> 23 #include <tegra_def.h> 24 #include <tegra_private.h> 25 26 extern uint64_t tegra_bl31_phys_base; 27 extern uint64_t tegra_sec_entry_point; 28 extern uint64_t tegra_console_base; 29 30 /* 31 * tegra_fake_system_suspend acts as a boolean var controlling whether 32 * we are going to take fake system suspend code or normal system suspend code 33 * path. This variable is set inside the sip call handlers,when the kernel 34 * requests a SIP call to set the suspend debug flags. 35 */ 36 uint8_t tegra_fake_system_suspend; 37 38 /* 39 * The following platform setup functions are weakly defined. They 40 * provide typical implementations that will be overridden by a SoC. 41 */ 42 #pragma weak tegra_soc_pwr_domain_suspend_pwrdown_early 43 #pragma weak tegra_soc_pwr_domain_suspend 44 #pragma weak tegra_soc_pwr_domain_on 45 #pragma weak tegra_soc_pwr_domain_off 46 #pragma weak tegra_soc_pwr_domain_on_finish 47 #pragma weak tegra_soc_pwr_domain_power_down_wfi 48 #pragma weak tegra_soc_prepare_system_reset 49 #pragma weak tegra_soc_prepare_system_off 50 #pragma weak tegra_soc_get_target_pwr_state 51 52 int tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state) 53 { 54 return PSCI_E_NOT_SUPPORTED; 55 } 56 57 int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) 58 { 59 return PSCI_E_NOT_SUPPORTED; 60 } 61 62 int tegra_soc_pwr_domain_on(u_register_t mpidr) 63 { 64 return PSCI_E_SUCCESS; 65 } 66 67 int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) 68 { 69 return PSCI_E_SUCCESS; 70 } 71 72 int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) 73 { 74 return PSCI_E_SUCCESS; 75 } 76 77 int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) 78 { 79 return PSCI_E_SUCCESS; 80 } 81 82 int tegra_soc_prepare_system_reset(void) 83 { 84 return PSCI_E_SUCCESS; 85 } 86 87 __dead2 void tegra_soc_prepare_system_off(void) 88 { 89 ERROR("Tegra System Off: operation not handled.\n"); 90 panic(); 91 } 92 93 plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, 94 const plat_local_state_t *states, 95 unsigned int ncpu) 96 { 97 plat_local_state_t target = PLAT_MAX_OFF_STATE, temp; 98 99 assert(ncpu); 100 101 do { 102 temp = *states++; 103 if ((temp < target)) 104 target = temp; 105 } while (--ncpu); 106 107 return target; 108 } 109 110 /******************************************************************************* 111 * This handler is called by the PSCI implementation during the `SYSTEM_SUSPEND` 112 * call to get the `power_state` parameter. This allows the platform to encode 113 * the appropriate State-ID field within the `power_state` parameter which can 114 * be utilized in `pwr_domain_suspend()` to suspend to system affinity level. 115 ******************************************************************************/ 116 void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state) 117 { 118 /* all affinities use system suspend state id */ 119 for (uint32_t i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) 120 req_state->pwr_domain_state[i] = PSTATE_ID_SOC_POWERDN; 121 } 122 123 /******************************************************************************* 124 * Handler called when an affinity instance is about to enter standby. 125 ******************************************************************************/ 126 void tegra_cpu_standby(plat_local_state_t cpu_state) 127 { 128 /* 129 * Enter standby state 130 * dsb is good practice before using wfi to enter low power states 131 */ 132 dsb(); 133 wfi(); 134 } 135 136 /******************************************************************************* 137 * Handler called when an affinity instance is about to be turned on. The 138 * level and mpidr determine the affinity instance. 139 ******************************************************************************/ 140 int tegra_pwr_domain_on(u_register_t mpidr) 141 { 142 return tegra_soc_pwr_domain_on(mpidr); 143 } 144 145 /******************************************************************************* 146 * Handler called when a power domain is about to be turned off. The 147 * target_state encodes the power state that each level should transition to. 148 ******************************************************************************/ 149 void tegra_pwr_domain_off(const psci_power_state_t *target_state) 150 { 151 tegra_soc_pwr_domain_off(target_state); 152 } 153 154 /******************************************************************************* 155 * Handler called when a power domain is about to be suspended. The 156 * target_state encodes the power state that each level should transition to. 157 * This handler is called with SMP and data cache enabled, when 158 * HW_ASSISTED_COHERENCY = 0 159 ******************************************************************************/ 160 void tegra_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state) 161 { 162 tegra_soc_pwr_domain_suspend_pwrdown_early(target_state); 163 } 164 165 /******************************************************************************* 166 * Handler called when a power domain is about to be suspended. The 167 * target_state encodes the power state that each level should transition to. 168 ******************************************************************************/ 169 void tegra_pwr_domain_suspend(const psci_power_state_t *target_state) 170 { 171 tegra_soc_pwr_domain_suspend(target_state); 172 173 /* Disable console if we are entering deep sleep. */ 174 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == 175 PSTATE_ID_SOC_POWERDN) 176 console_uninit(); 177 178 /* disable GICC */ 179 tegra_gic_cpuif_deactivate(); 180 } 181 182 /******************************************************************************* 183 * Handler called at the end of the power domain suspend sequence. The 184 * target_state encodes the power state that each level should transition to. 185 ******************************************************************************/ 186 __dead2 void tegra_pwr_domain_power_down_wfi(const psci_power_state_t 187 *target_state) 188 { 189 uint8_t pwr_state = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]; 190 uint64_t rmr_el3 = 0; 191 192 /* call the chip's power down handler */ 193 tegra_soc_pwr_domain_power_down_wfi(target_state); 194 195 /* 196 * If we are in fake system suspend mode, ensure we start doing 197 * procedures that help in looping back towards system suspend exit 198 * instead of calling WFI by requesting a warm reset. 199 * Else, just call WFI to enter low power state. 200 */ 201 if ((tegra_fake_system_suspend != 0U) && 202 (pwr_state == (uint8_t)PSTATE_ID_SOC_POWERDN)) { 203 204 /* warm reboot */ 205 rmr_el3 = read_rmr_el3(); 206 write_rmr_el3(rmr_el3 | RMR_WARM_RESET_CPU); 207 208 } else { 209 /* enter power down state */ 210 wfi(); 211 } 212 213 /* we can never reach here */ 214 panic(); 215 } 216 217 /******************************************************************************* 218 * Handler called when a power domain has just been powered on after 219 * being turned off earlier. The target_state encodes the low power state that 220 * each level has woken up from. 221 ******************************************************************************/ 222 void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state) 223 { 224 plat_params_from_bl2_t *plat_params; 225 226 /* 227 * Initialize the GIC cpu and distributor interfaces 228 */ 229 plat_gic_setup(); 230 231 /* 232 * Check if we are exiting from deep sleep. 233 */ 234 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == 235 PSTATE_ID_SOC_POWERDN) { 236 237 /* Initialize the runtime console */ 238 if (tegra_console_base != (uint64_t)0) { 239 console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ, 240 TEGRA_CONSOLE_BAUDRATE); 241 } 242 243 /* 244 * Restore Memory Controller settings as it loses state 245 * during system suspend. 246 */ 247 tegra_memctrl_restore_settings(); 248 249 /* 250 * Security configuration to allow DRAM/device access. 251 */ 252 plat_params = bl31_get_plat_params(); 253 tegra_memctrl_tzdram_setup(plat_params->tzdram_base, 254 plat_params->tzdram_size); 255 256 /* 257 * Set up the TZRAM memory aperture to allow only secure world 258 * access 259 */ 260 tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE); 261 } 262 263 /* 264 * Reset hardware settings. 265 */ 266 tegra_soc_pwr_domain_on_finish(target_state); 267 } 268 269 /******************************************************************************* 270 * Handler called when a power domain has just been powered on after 271 * having been suspended earlier. The target_state encodes the low power state 272 * that each level has woken up from. 273 ******************************************************************************/ 274 void tegra_pwr_domain_suspend_finish(const psci_power_state_t *target_state) 275 { 276 tegra_pwr_domain_on_finish(target_state); 277 } 278 279 /******************************************************************************* 280 * Handler called when the system wants to be powered off 281 ******************************************************************************/ 282 __dead2 void tegra_system_off(void) 283 { 284 INFO("Powering down system...\n"); 285 286 tegra_soc_prepare_system_off(); 287 } 288 289 /******************************************************************************* 290 * Handler called when the system wants to be restarted. 291 ******************************************************************************/ 292 __dead2 void tegra_system_reset(void) 293 { 294 INFO("Restarting system...\n"); 295 296 /* per-SoC system reset handler */ 297 tegra_soc_prepare_system_reset(); 298 299 /* 300 * Program the PMC in order to restart the system. 301 */ 302 tegra_pmc_system_reset(); 303 } 304 305 /******************************************************************************* 306 * Handler called to check the validity of the power state parameter. 307 ******************************************************************************/ 308 int32_t tegra_validate_power_state(unsigned int power_state, 309 psci_power_state_t *req_state) 310 { 311 assert(req_state); 312 313 return tegra_soc_validate_power_state(power_state, req_state); 314 } 315 316 /******************************************************************************* 317 * Platform handler called to check the validity of the non secure entrypoint. 318 ******************************************************************************/ 319 int tegra_validate_ns_entrypoint(uintptr_t entrypoint) 320 { 321 /* 322 * Check if the non secure entrypoint lies within the non 323 * secure DRAM. 324 */ 325 if ((entrypoint >= TEGRA_DRAM_BASE) && (entrypoint <= TEGRA_DRAM_END)) 326 return PSCI_E_SUCCESS; 327 328 return PSCI_E_INVALID_ADDRESS; 329 } 330 331 /******************************************************************************* 332 * Export the platform handlers to enable psci to invoke them 333 ******************************************************************************/ 334 static const plat_psci_ops_t tegra_plat_psci_ops = { 335 .cpu_standby = tegra_cpu_standby, 336 .pwr_domain_on = tegra_pwr_domain_on, 337 .pwr_domain_off = tegra_pwr_domain_off, 338 .pwr_domain_suspend_pwrdown_early = tegra_pwr_domain_suspend_pwrdown_early, 339 .pwr_domain_suspend = tegra_pwr_domain_suspend, 340 .pwr_domain_on_finish = tegra_pwr_domain_on_finish, 341 .pwr_domain_suspend_finish = tegra_pwr_domain_suspend_finish, 342 .pwr_domain_pwr_down_wfi = tegra_pwr_domain_power_down_wfi, 343 .system_off = tegra_system_off, 344 .system_reset = tegra_system_reset, 345 .validate_power_state = tegra_validate_power_state, 346 .validate_ns_entrypoint = tegra_validate_ns_entrypoint, 347 .get_sys_suspend_power_state = tegra_get_sys_suspend_power_state, 348 }; 349 350 /******************************************************************************* 351 * Export the platform specific power ops and initialize Power Controller 352 ******************************************************************************/ 353 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 354 const plat_psci_ops_t **psci_ops) 355 { 356 psci_power_state_t target_state = { { PSCI_LOCAL_STATE_RUN } }; 357 358 /* 359 * Flush entrypoint variable to PoC since it will be 360 * accessed after a reset with the caches turned off. 361 */ 362 tegra_sec_entry_point = sec_entrypoint; 363 flush_dcache_range((uint64_t)&tegra_sec_entry_point, sizeof(uint64_t)); 364 365 /* 366 * Reset hardware settings. 367 */ 368 tegra_soc_pwr_domain_on_finish(&target_state); 369 370 /* 371 * Initialize PSCI ops struct 372 */ 373 *psci_ops = &tegra_plat_psci_ops; 374 375 return 0; 376 } 377 378 /******************************************************************************* 379 * Platform handler to calculate the proper target power level at the 380 * specified affinity level 381 ******************************************************************************/ 382 plat_local_state_t plat_get_target_pwr_state(unsigned int lvl, 383 const plat_local_state_t *states, 384 unsigned int ncpu) 385 { 386 return tegra_soc_get_target_pwr_state(lvl, states, ncpu); 387 } 388