1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch.h> 12 #include <bl1/bl1.h> 13 #include <common/bl_common.h> 14 #include <drivers/arm/sp805.h> 15 #include <lib/utils.h> 16 #include <lib/xlat_tables/xlat_tables_compat.h> 17 #include <plat/common/platform.h> 18 19 #include <arm_def.h> 20 #include <plat_arm.h> 21 22 #include "../../../bl1/bl1_private.h" 23 24 /* Weak definitions may be overridden in specific ARM standard platform */ 25 #pragma weak bl1_early_platform_setup 26 #pragma weak bl1_plat_arch_setup 27 #pragma weak bl1_platform_setup 28 #pragma weak bl1_plat_sec_mem_layout 29 #pragma weak bl1_plat_prepare_exit 30 #pragma weak bl1_plat_get_next_image_id 31 #pragma weak plat_arm_bl1_fwu_needed 32 33 #define MAP_BL1_TOTAL MAP_REGION_FLAT( \ 34 bl1_tzram_layout.total_base, \ 35 bl1_tzram_layout.total_size, \ 36 MT_MEMORY | MT_RW | MT_SECURE) 37 /* 38 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section 39 * otherwise one region is defined containing both 40 */ 41 #if SEPARATE_CODE_AND_RODATA 42 #define MAP_BL1_RO MAP_REGION_FLAT( \ 43 BL_CODE_BASE, \ 44 BL1_CODE_END - BL_CODE_BASE, \ 45 MT_CODE | MT_SECURE), \ 46 MAP_REGION_FLAT( \ 47 BL1_RO_DATA_BASE, \ 48 BL1_RO_DATA_END \ 49 - BL_RO_DATA_BASE, \ 50 MT_RO_DATA | MT_SECURE) 51 #else 52 #define MAP_BL1_RO MAP_REGION_FLAT( \ 53 BL_CODE_BASE, \ 54 BL1_CODE_END - BL_CODE_BASE, \ 55 MT_CODE | MT_SECURE) 56 #endif 57 58 /* Data structure which holds the extents of the trusted SRAM for BL1*/ 59 static meminfo_t bl1_tzram_layout; 60 61 struct meminfo *bl1_plat_sec_mem_layout(void) 62 { 63 return &bl1_tzram_layout; 64 } 65 66 /******************************************************************************* 67 * BL1 specific platform actions shared between ARM standard platforms. 68 ******************************************************************************/ 69 void arm_bl1_early_platform_setup(void) 70 { 71 72 #if !ARM_DISABLE_TRUSTED_WDOG 73 /* Enable watchdog */ 74 sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL); 75 #endif 76 77 /* Initialize the console to provide early debug support */ 78 arm_console_boot_init(); 79 80 /* Allow BL1 to see the whole Trusted RAM */ 81 bl1_tzram_layout.total_base = ARM_BL_RAM_BASE; 82 bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE; 83 } 84 85 void bl1_early_platform_setup(void) 86 { 87 arm_bl1_early_platform_setup(); 88 89 /* 90 * Initialize Interconnect for this cluster during cold boot. 91 * No need for locks as no other CPU is active. 92 */ 93 plat_arm_interconnect_init(); 94 /* 95 * Enable Interconnect coherency for the primary CPU's cluster. 96 */ 97 plat_arm_interconnect_enter_coherency(); 98 } 99 100 /****************************************************************************** 101 * Perform the very early platform specific architecture setup shared between 102 * ARM standard platforms. This only does basic initialization. Later 103 * architectural setup (bl1_arch_setup()) does not do anything platform 104 * specific. 105 *****************************************************************************/ 106 void arm_bl1_plat_arch_setup(void) 107 { 108 #if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG 109 /* 110 * Ensure ARM platforms don't use coherent memory in BL1 unless 111 * cryptocell integration is enabled. 112 */ 113 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); 114 #endif 115 116 const mmap_region_t bl_regions[] = { 117 MAP_BL1_TOTAL, 118 MAP_BL1_RO, 119 #if USE_ROMLIB 120 ARM_MAP_ROMLIB_CODE, 121 ARM_MAP_ROMLIB_DATA, 122 #endif 123 #if ARM_CRYPTOCELL_INTEG 124 ARM_MAP_BL_COHERENT_RAM, 125 #endif 126 {0} 127 }; 128 129 setup_page_tables(bl_regions, plat_arm_get_mmap()); 130 #ifdef AARCH32 131 enable_mmu_svc_mon(0); 132 #else 133 enable_mmu_el3(0); 134 #endif /* AARCH32 */ 135 136 arm_setup_romlib(); 137 } 138 139 void bl1_plat_arch_setup(void) 140 { 141 arm_bl1_plat_arch_setup(); 142 } 143 144 /* 145 * Perform the platform specific architecture setup shared between 146 * ARM standard platforms. 147 */ 148 void arm_bl1_platform_setup(void) 149 { 150 /* Initialise the IO layer and register platform IO devices */ 151 plat_arm_io_setup(); 152 arm_load_tb_fw_config(); 153 #if TRUSTED_BOARD_BOOT 154 /* Share the Mbed TLS heap info with other images */ 155 arm_bl1_set_mbedtls_heap(); 156 #endif /* TRUSTED_BOARD_BOOT */ 157 158 /* 159 * Allow access to the System counter timer module and program 160 * counter frequency for non secure images during FWU 161 */ 162 arm_configure_sys_timer(); 163 write_cntfrq_el0(plat_get_syscnt_freq2()); 164 } 165 166 void bl1_platform_setup(void) 167 { 168 arm_bl1_platform_setup(); 169 } 170 171 void bl1_plat_prepare_exit(entry_point_info_t *ep_info) 172 { 173 #if !ARM_DISABLE_TRUSTED_WDOG 174 /* Disable watchdog before leaving BL1 */ 175 sp805_stop(ARM_SP805_TWDG_BASE); 176 #endif 177 178 #ifdef EL3_PAYLOAD_BASE 179 /* 180 * Program the EL3 payload's entry point address into the CPUs mailbox 181 * in order to release secondary CPUs from their holding pen and make 182 * them jump there. 183 */ 184 plat_arm_program_trusted_mailbox(ep_info->pc); 185 dsbsy(); 186 sev(); 187 #endif 188 } 189 190 /* 191 * On Arm platforms, the FWU process is triggered when the FIP image has 192 * been tampered with. 193 */ 194 int plat_arm_bl1_fwu_needed(void) 195 { 196 return (arm_io_is_toc_valid() != 1); 197 } 198 199 /******************************************************************************* 200 * The following function checks if Firmware update is needed, 201 * by checking if TOC in FIP image is valid or not. 202 ******************************************************************************/ 203 unsigned int bl1_plat_get_next_image_id(void) 204 { 205 if (plat_arm_bl1_fwu_needed() != 0) 206 return NS_BL1U_IMAGE_ID; 207 208 return BL2_IMAGE_ID; 209 } 210