1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __TEGRA_DEF_H__ 8 #define __TEGRA_DEF_H__ 9 10 /******************************************************************************* 11 * MCE apertures used by the ARI interface 12 * 13 * Aperture 0 - Cpu0 (ARM Cortex A-57) 14 * Aperture 1 - Cpu1 (ARM Cortex A-57) 15 * Aperture 2 - Cpu2 (ARM Cortex A-57) 16 * Aperture 3 - Cpu3 (ARM Cortex A-57) 17 * Aperture 4 - Cpu4 (Denver15) 18 * Aperture 5 - Cpu5 (Denver15) 19 ******************************************************************************/ 20 #define MCE_ARI_APERTURE_0_OFFSET 0x0 21 #define MCE_ARI_APERTURE_1_OFFSET 0x10000 22 #define MCE_ARI_APERTURE_2_OFFSET 0x20000 23 #define MCE_ARI_APERTURE_3_OFFSET 0x30000 24 #define MCE_ARI_APERTURE_4_OFFSET 0x40000 25 #define MCE_ARI_APERTURE_5_OFFSET 0x50000 26 #define MCE_ARI_APERTURE_OFFSET_MAX MCE_APERTURE_5_OFFSET 27 28 /* number of apertures */ 29 #define MCE_ARI_APERTURES_MAX 6 30 31 /* each ARI aperture is 64KB */ 32 #define MCE_ARI_APERTURE_SIZE 0x10000 33 34 /******************************************************************************* 35 * CPU core id macros for the MCE_ONLINE_CORE ARI 36 ******************************************************************************/ 37 #define MCE_CORE_ID_MAX 8 38 #define MCE_CORE_ID_MASK 0x7 39 40 /******************************************************************************* 41 * These values are used by the PSCI implementation during the `CPU_SUSPEND` 42 * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' 43 * parameter. 44 ******************************************************************************/ 45 #define PSTATE_ID_CORE_IDLE 6 46 #define PSTATE_ID_CORE_POWERDN 7 47 #define PSTATE_ID_SOC_POWERDN 2 48 49 /******************************************************************************* 50 * Platform power states (used by PSCI framework) 51 * 52 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID 53 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID 54 ******************************************************************************/ 55 #define PLAT_MAX_RET_STATE 1 56 #define PLAT_MAX_OFF_STATE 8 57 58 /******************************************************************************* 59 * Implementation defined ACTLR_EL3 bit definitions 60 ******************************************************************************/ 61 #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 62 #define ACTLR_EL3_L2ECTLR_BIT (1 << 5) 63 #define ACTLR_EL3_L2CTLR_BIT (1 << 4) 64 #define ACTLR_EL3_CPUECTLR_BIT (1 << 1) 65 #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 66 #define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ 67 ACTLR_EL3_L2ECTLR_BIT | \ 68 ACTLR_EL3_L2CTLR_BIT | \ 69 ACTLR_EL3_CPUECTLR_BIT | \ 70 ACTLR_EL3_CPUACTLR_BIT) 71 72 /******************************************************************************* 73 * Secure IRQ definitions 74 ******************************************************************************/ 75 #define TEGRA186_TOP_WDT_IRQ 49 76 #define TEGRA186_AON_WDT_IRQ 50 77 78 #define TEGRA186_SEC_IRQ_TARGET_MASK 0xF3 /* 4 A57 - 2 Denver */ 79 80 /******************************************************************************* 81 * Tegra Miscellanous register constants 82 ******************************************************************************/ 83 #define TEGRA_MISC_BASE 0x00100000 84 #define HARDWARE_REVISION_OFFSET 0x4 85 86 #define MISCREG_PFCFG 0x200C 87 88 /******************************************************************************* 89 * Tegra TSA Controller constants 90 ******************************************************************************/ 91 #define TEGRA_TSA_BASE 0x02400000 92 93 /******************************************************************************* 94 * TSA configuration registers 95 ******************************************************************************/ 96 #define TSA_CONFIG_STATIC0_CSW_SESWR 0x4010 97 #define TSA_CONFIG_STATIC0_CSW_SESWR_RESET 0x1100 98 #define TSA_CONFIG_STATIC0_CSW_ETRW 0x4038 99 #define TSA_CONFIG_STATIC0_CSW_ETRW_RESET 0x1100 100 #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB 0x5010 101 #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET 0x1100 102 #define TSA_CONFIG_STATIC0_CSW_AXISW 0x7008 103 #define TSA_CONFIG_STATIC0_CSW_AXISW_RESET 0x1100 104 #define TSA_CONFIG_STATIC0_CSW_HDAW 0xA008 105 #define TSA_CONFIG_STATIC0_CSW_HDAW_RESET 0x100 106 #define TSA_CONFIG_STATIC0_CSW_AONDMAW 0xB018 107 #define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET 0x1100 108 #define TSA_CONFIG_STATIC0_CSW_SCEDMAW 0xD018 109 #define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET 0x1100 110 #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW 0xD028 111 #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET 0x1100 112 #define TSA_CONFIG_STATIC0_CSW_APEDMAW 0x12018 113 #define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET 0x1100 114 #define TSA_CONFIG_STATIC0_CSW_UFSHCW 0x13008 115 #define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET 0x1100 116 #define TSA_CONFIG_STATIC0_CSW_AFIW 0x13018 117 #define TSA_CONFIG_STATIC0_CSW_AFIW_RESET 0x1100 118 #define TSA_CONFIG_STATIC0_CSW_SATAW 0x13028 119 #define TSA_CONFIG_STATIC0_CSW_SATAW_RESET 0x1100 120 #define TSA_CONFIG_STATIC0_CSW_EQOSW 0x13038 121 #define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET 0x1100 122 #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW 0x15008 123 #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET 0x1100 124 #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW 0x15018 125 #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET 0x1100 126 127 #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (0x3 << 11) 128 #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (0 << 11) 129 130 /******************************************************************************* 131 * Tegra Memory Controller constants 132 ******************************************************************************/ 133 #define TEGRA_MC_STREAMID_BASE 0x02C00000 134 #define TEGRA_MC_BASE 0x02C10000 135 136 /* General Security Carveout register macros */ 137 #define MC_GSC_CONFIG_REGS_SIZE 0x40UL 138 #define MC_GSC_LOCK_CFG_SETTINGS_BIT (1UL << 1) 139 #define MC_GSC_ENABLE_TZ_LOCK_BIT (1UL << 0) 140 #define MC_GSC_SIZE_RANGE_4KB_SHIFT 27UL 141 #define MC_GSC_BASE_LO_SHIFT 12UL 142 #define MC_GSC_BASE_LO_MASK 0xFFFFFUL 143 #define MC_GSC_BASE_HI_SHIFT 0UL 144 #define MC_GSC_BASE_HI_MASK 3UL 145 146 /* TZDRAM carveout configuration registers */ 147 #define MC_SECURITY_CFG0_0 0x70 148 #define MC_SECURITY_CFG1_0 0x74 149 #define MC_SECURITY_CFG3_0 0x9BC 150 151 /* Video Memory carveout configuration registers */ 152 #define MC_VIDEO_PROTECT_BASE_HI 0x978 153 #define MC_VIDEO_PROTECT_BASE_LO 0x648 154 #define MC_VIDEO_PROTECT_SIZE_MB 0x64C 155 156 /* 157 * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the 158 * non-overlapping Video memory region 159 */ 160 #define MC_VIDEO_PROTECT_CLEAR_CFG 0x25A0 161 #define MC_VIDEO_PROTECT_CLEAR_BASE_LO 0x25A4 162 #define MC_VIDEO_PROTECT_CLEAR_BASE_HI 0x25A8 163 #define MC_VIDEO_PROTECT_CLEAR_SIZE 0x25AC 164 #define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 0x25B0 165 166 /* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */ 167 #define MC_TZRAM_CARVEOUT_CFG 0x2190 168 #define MC_TZRAM_BASE_LO 0x2194 169 #define MC_TZRAM_BASE_HI 0x2198 170 #define MC_TZRAM_SIZE 0x219C 171 #define MC_TZRAM_CLIENT_ACCESS_CFG0 0x21A0 172 173 /******************************************************************************* 174 * Tegra UART Controller constants 175 ******************************************************************************/ 176 #define TEGRA_UARTA_BASE 0x03100000 177 #define TEGRA_UARTB_BASE 0x03110000 178 #define TEGRA_UARTC_BASE 0x0C280000 179 #define TEGRA_UARTD_BASE 0x03130000 180 #define TEGRA_UARTE_BASE 0x03140000 181 #define TEGRA_UARTF_BASE 0x03150000 182 #define TEGRA_UARTG_BASE 0x0C290000 183 184 /******************************************************************************* 185 * Tegra Fuse Controller related constants 186 ******************************************************************************/ 187 #define TEGRA_FUSE_BASE 0x03820000 188 #define OPT_SUBREVISION 0x248 189 #define SUBREVISION_MASK 0xFF 190 191 /******************************************************************************* 192 * GICv2 & interrupt handling related constants 193 ******************************************************************************/ 194 #define TEGRA_GICD_BASE 0x03881000 195 #define TEGRA_GICC_BASE 0x03882000 196 197 /******************************************************************************* 198 * Security Engine related constants 199 ******************************************************************************/ 200 #define TEGRA_SE0_BASE 0x03AC0000 201 #define SE_MUTEX_WATCHDOG_NS_LIMIT 0x6C 202 #define TEGRA_PKA1_BASE 0x03AD0000 203 #define PKA_MUTEX_WATCHDOG_NS_LIMIT 0x8144 204 #define TEGRA_RNG1_BASE 0x03AE0000 205 #define RNG_MUTEX_WATCHDOG_NS_LIMIT 0xFE0 206 207 /******************************************************************************* 208 * Tegra Clock and Reset Controller constants 209 ******************************************************************************/ 210 #define TEGRA_CAR_RESET_BASE 0x05000000 211 212 /******************************************************************************* 213 * Tegra micro-seconds timer constants 214 ******************************************************************************/ 215 #define TEGRA_TMRUS_BASE 0x0C2E0000 216 #define TEGRA_TMRUS_SIZE 0x1000 217 218 /******************************************************************************* 219 * Tegra Power Mgmt Controller constants 220 ******************************************************************************/ 221 #define TEGRA_PMC_BASE 0x0C360000 222 223 /******************************************************************************* 224 * Tegra scratch registers constants 225 ******************************************************************************/ 226 #define TEGRA_SCRATCH_BASE 0x0C390000 227 #define SECURE_SCRATCH_RSV1_LO 0x658 228 #define SECURE_SCRATCH_RSV1_HI 0x65C 229 #define SECURE_SCRATCH_RSV6 0x680 230 #define SECURE_SCRATCH_RSV11_LO 0x6A8 231 #define SECURE_SCRATCH_RSV11_HI 0x6AC 232 #define SECURE_SCRATCH_RSV53_LO 0x7F8 233 #define SECURE_SCRATCH_RSV53_HI 0x7FC 234 #define SECURE_SCRATCH_RSV54_HI 0x804 235 #define SECURE_SCRATCH_RSV55_LO 0x808 236 #define SECURE_SCRATCH_RSV55_HI 0x80C 237 238 /******************************************************************************* 239 * Tegra Memory Mapped Control Register Access constants 240 ******************************************************************************/ 241 #define TEGRA_MMCRAB_BASE 0x0E000000 242 243 /******************************************************************************* 244 * Tegra Memory Mapped Activity Monitor Register Access constants 245 ******************************************************************************/ 246 #define TEGRA_ARM_ACTMON_CTR_BASE 0x0E060000 247 #define TEGRA_DENVER_ACTMON_CTR_BASE 0x0E070000 248 249 /******************************************************************************* 250 * Tegra SMMU Controller constants 251 ******************************************************************************/ 252 #define TEGRA_SMMU0_BASE 0x12000000 253 254 /******************************************************************************* 255 * Tegra TZRAM constants 256 ******************************************************************************/ 257 #define TEGRA_TZRAM_BASE 0x30000000 258 #define TEGRA_TZRAM_SIZE 0x40000 259 260 #endif /* __TEGRA_DEF_H__ */ 261