1 /* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __PL011_H__ 32 #define __PL011_H__ 33 34 #include <mmio.h> 35 36 37 /* PL011 Registers */ 38 #define UARTDR 0x000 39 #define UARTRSR 0x004 40 #define UARTECR 0x004 41 #define UARTFR 0x018 42 #define UARTILPR 0x020 43 #define UARTIBRD 0x024 44 #define UARTFBRD 0x028 45 #define UARTLCR_H 0x02C 46 #define UARTCR 0x030 47 #define UARTIFLS 0x034 48 #define UARTIMSC 0x038 49 #define UARTRIS 0x03C 50 #define UARTMIS 0x040 51 #define UARTICR 0x044 52 #define UARTDMACR 0x048 53 54 /* Data status bits */ 55 #define UART_DATA_ERROR_MASK 0x0F00 56 57 /* Status reg bits */ 58 #define UART_STATUS_ERROR_MASK 0x0F 59 60 /* Flag reg bits */ 61 #define PL011_UARTFR_RI (1 << 8) /* Ring indicator */ 62 #define PL011_UARTFR_TXFE (1 << 7) /* Transmit FIFO empty */ 63 #define PL011_UARTFR_RXFF (1 << 6) /* Receive FIFO full */ 64 #define PL011_UARTFR_TXFF (1 << 5) /* Transmit FIFO full */ 65 #define PL011_UARTFR_RXFE (1 << 4) /* Receive FIFO empty */ 66 #define PL011_UARTFR_BUSY (1 << 3) /* UART busy */ 67 #define PL011_UARTFR_DCD (1 << 2) /* Data carrier detect */ 68 #define PL011_UARTFR_DSR (1 << 1) /* Data set ready */ 69 #define PL011_UARTFR_CTS (1 << 0) /* Clear to send */ 70 71 /* Control reg bits */ 72 #define PL011_UARTCR_CTSEN (1 << 15) /* CTS hardware flow control enable */ 73 #define PL011_UARTCR_RTSEN (1 << 14) /* RTS hardware flow control enable */ 74 #define PL011_UARTCR_RTS (1 << 11) /* Request to send */ 75 #define PL011_UARTCR_DTR (1 << 10) /* Data transmit ready. */ 76 #define PL011_UARTCR_RXE (1 << 9) /* Receive enable */ 77 #define PL011_UARTCR_TXE (1 << 8) /* Transmit enable */ 78 #define PL011_UARTCR_LBE (1 << 7) /* Loopback enable */ 79 #define PL011_UARTCR_UARTEN (1 << 0) /* UART Enable */ 80 81 #if !defined(PL011_BAUDRATE) 82 #define PL011_BAUDRATE 115200 83 #endif 84 85 #if !defined(PL011_CLK_IN_HZ) 86 #define PL011_CLK_IN_HZ 24000000 87 #endif 88 89 #if !defined(PL011_LINE_CONTROL) 90 /* FIFO Enabled / No Parity / 8 Data bit / One Stop Bit */ 91 #define PL011_LINE_CONTROL (PL011_UARTLCR_H_FEN | PL011_UARTLCR_H_WLEN_8) 92 #endif 93 94 /* Line Control Register Bits */ 95 #define PL011_UARTLCR_H_SPS (1 << 7) /* Stick parity select */ 96 #define PL011_UARTLCR_H_WLEN_8 (3 << 5) 97 #define PL011_UARTLCR_H_WLEN_7 (2 << 5) 98 #define PL011_UARTLCR_H_WLEN_6 (1 << 5) 99 #define PL011_UARTLCR_H_WLEN_5 (0 << 5) 100 #define PL011_UARTLCR_H_FEN (1 << 4) /* FIFOs Enable */ 101 #define PL011_UARTLCR_H_STP2 (1 << 3) /* Two stop bits select */ 102 #define PL011_UARTLCR_H_EPS (1 << 2) /* Even parity select */ 103 #define PL011_UARTLCR_H_PEN (1 << 1) /* Parity Enable */ 104 #define PL011_UARTLCR_H_BRK (1 << 0) /* Send break */ 105 106 /******************************************************************************* 107 * Pl011 CPU interface accessors for writing registers 108 ******************************************************************************/ 109 110 static inline void pl011_write_ibrd(unsigned long base, unsigned int val) 111 { 112 mmio_write_32(base + UARTIBRD, val); 113 } 114 115 static inline void pl011_write_fbrd(unsigned long base, unsigned int val) 116 { 117 mmio_write_32(base + UARTFBRD, val); 118 } 119 120 static inline void pl011_write_lcr_h(unsigned long base, unsigned int val) 121 { 122 mmio_write_32(base + UARTLCR_H, val); 123 } 124 125 static inline void pl011_write_ecr(unsigned long base, unsigned int val) 126 { 127 mmio_write_32(base + UARTECR, val); 128 } 129 130 static inline void pl011_write_cr(unsigned long base, unsigned int val) 131 { 132 mmio_write_32(base + UARTCR, val); 133 } 134 135 static inline void pl011_write_dr(unsigned long base, unsigned int val) 136 { 137 mmio_write_32(base + UARTDR, val); 138 } 139 140 /******************************************************************************* 141 * Pl011 CPU interface accessors for reading registers 142 ******************************************************************************/ 143 144 static inline unsigned int pl011_read_fr(unsigned long base) 145 { 146 return mmio_read_32(base + UARTFR); 147 } 148 149 static inline unsigned int pl011_read_dr(unsigned long base) 150 { 151 return mmio_read_32(base + UARTDR); 152 } 153 154 /******************************************************************************* 155 * Function prototypes 156 ******************************************************************************/ 157 158 void pl011_setbaudrate(unsigned long base_addr, unsigned int baudrate); 159 160 #endif /* __PL011_H__ */ 161