1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <bl_common.h> 8 #include <gicv3.h> 9 #include <interrupt_props.h> 10 #include <platform.h> 11 #include <platform_def.h> 12 #include <utils.h> 13 14 /****************************************************************************** 15 * The following functions are defined as weak to allow a platform to override 16 * the way the GICv3 driver is initialised and used. 17 *****************************************************************************/ 18 #pragma weak plat_rockchip_gic_driver_init 19 #pragma weak plat_rockchip_gic_init 20 #pragma weak plat_rockchip_gic_cpuif_enable 21 #pragma weak plat_rockchip_gic_cpuif_disable 22 #pragma weak plat_rockchip_gic_pcpu_init 23 24 /* The GICv3 driver only needs to be initialized in EL3 */ 25 uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; 26 27 static const interrupt_prop_t g01s_interrupt_props[] = { 28 PLAT_RK_GICV3_G0_IRQS, 29 PLAT_RK_GICV3_G1S_IRQS 30 }; 31 32 static unsigned int plat_rockchip_mpidr_to_core_pos(unsigned long mpidr) 33 { 34 return (unsigned int)plat_core_pos_by_mpidr(mpidr); 35 } 36 37 const gicv3_driver_data_t rockchip_gic_data = { 38 .gicd_base = PLAT_RK_GICD_BASE, 39 .gicr_base = PLAT_RK_GICR_BASE, 40 .interrupt_props = g01s_interrupt_props, 41 .interrupt_props_num = ARRAY_SIZE(g01s_interrupt_props), 42 .rdistif_num = PLATFORM_CORE_COUNT, 43 .rdistif_base_addrs = rdistif_base_addrs, 44 .mpidr_to_core_pos = plat_rockchip_mpidr_to_core_pos, 45 }; 46 47 void plat_rockchip_gic_driver_init(void) 48 { 49 /* 50 * The GICv3 driver is initialized in EL3 and does not need 51 * to be initialized again in SEL1. This is because the S-EL1 52 * can use GIC system registers to manage interrupts and does 53 * not need GIC interface base addresses to be configured. 54 */ 55 #ifdef IMAGE_BL31 56 gicv3_driver_init(&rockchip_gic_data); 57 #endif 58 } 59 60 /****************************************************************************** 61 * RockChip common helper to initialize the GIC. Only invoked 62 * by BL31 63 *****************************************************************************/ 64 void plat_rockchip_gic_init(void) 65 { 66 gicv3_distif_init(); 67 gicv3_rdistif_init(plat_my_core_pos()); 68 gicv3_cpuif_enable(plat_my_core_pos()); 69 } 70 71 /****************************************************************************** 72 * RockChip common helper to enable the GIC CPU interface 73 *****************************************************************************/ 74 void plat_rockchip_gic_cpuif_enable(void) 75 { 76 gicv3_cpuif_enable(plat_my_core_pos()); 77 } 78 79 /****************************************************************************** 80 * RockChip common helper to disable the GIC CPU interface 81 *****************************************************************************/ 82 void plat_rockchip_gic_cpuif_disable(void) 83 { 84 gicv3_cpuif_disable(plat_my_core_pos()); 85 } 86 87 /****************************************************************************** 88 * RockChip common helper to initialize the per-cpu redistributor interface 89 * in GICv3 90 *****************************************************************************/ 91 void plat_rockchip_gic_pcpu_init(void) 92 { 93 gicv3_rdistif_init(plat_my_core_pos()); 94 } 95