1 /* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PSCI_H__ 8 #define __PSCI_H__ 9 10 #include <bakery_lock.h> 11 #include <bl_common.h> 12 #include <platform_def.h> /* for PLAT_NUM_PWR_DOMAINS */ 13 #if ENABLE_PLAT_COMPAT 14 #include <psci_compat.h> 15 #endif 16 #include <psci_lib.h> /* To maintain compatibility for SPDs */ 17 18 /******************************************************************************* 19 * Number of power domains whose state this PSCI implementation can track 20 ******************************************************************************/ 21 #ifdef PLAT_NUM_PWR_DOMAINS 22 #define PSCI_NUM_PWR_DOMAINS PLAT_NUM_PWR_DOMAINS 23 #else 24 #define PSCI_NUM_PWR_DOMAINS (2 * PLATFORM_CORE_COUNT) 25 #endif 26 27 #define PSCI_NUM_NON_CPU_PWR_DOMAINS (PSCI_NUM_PWR_DOMAINS - \ 28 PLATFORM_CORE_COUNT) 29 30 /* This is the power level corresponding to a CPU */ 31 #define PSCI_CPU_PWR_LVL 0 32 33 /* 34 * The maximum power level supported by PSCI. Since PSCI CPU_SUSPEND 35 * uses the old power_state parameter format which has 2 bits to specify the 36 * power level, this constant is defined to be 3. 37 */ 38 #define PSCI_MAX_PWR_LVL 3 39 40 /******************************************************************************* 41 * Defines for runtime services function ids 42 ******************************************************************************/ 43 #define PSCI_VERSION 0x84000000 44 #define PSCI_CPU_SUSPEND_AARCH32 0x84000001 45 #define PSCI_CPU_SUSPEND_AARCH64 0xc4000001 46 #define PSCI_CPU_OFF 0x84000002 47 #define PSCI_CPU_ON_AARCH32 0x84000003 48 #define PSCI_CPU_ON_AARCH64 0xc4000003 49 #define PSCI_AFFINITY_INFO_AARCH32 0x84000004 50 #define PSCI_AFFINITY_INFO_AARCH64 0xc4000004 51 #define PSCI_MIG_AARCH32 0x84000005 52 #define PSCI_MIG_AARCH64 0xc4000005 53 #define PSCI_MIG_INFO_TYPE 0x84000006 54 #define PSCI_MIG_INFO_UP_CPU_AARCH32 0x84000007 55 #define PSCI_MIG_INFO_UP_CPU_AARCH64 0xc4000007 56 #define PSCI_SYSTEM_OFF 0x84000008 57 #define PSCI_SYSTEM_RESET 0x84000009 58 #define PSCI_FEATURES 0x8400000A 59 #define PSCI_NODE_HW_STATE_AARCH32 0x8400000d 60 #define PSCI_NODE_HW_STATE_AARCH64 0xc400000d 61 #define PSCI_SYSTEM_SUSPEND_AARCH32 0x8400000E 62 #define PSCI_SYSTEM_SUSPEND_AARCH64 0xc400000E 63 #define PSCI_STAT_RESIDENCY_AARCH32 0x84000010 64 #define PSCI_STAT_RESIDENCY_AARCH64 0xc4000010 65 #define PSCI_STAT_COUNT_AARCH32 0x84000011 66 #define PSCI_STAT_COUNT_AARCH64 0xc4000011 67 68 /* Macro to help build the psci capabilities bitfield */ 69 #define define_psci_cap(x) (1 << (x & 0x1f)) 70 71 /* 72 * Number of PSCI calls (above) implemented 73 */ 74 #if ENABLE_PSCI_STAT 75 #define PSCI_NUM_CALLS 22 76 #else 77 #define PSCI_NUM_CALLS 18 78 #endif 79 80 /* The macros below are used to identify PSCI calls from the SMC function ID */ 81 #define PSCI_FID_MASK 0xffe0u 82 #define PSCI_FID_VALUE 0u 83 #define is_psci_fid(_fid) \ 84 (((_fid) & PSCI_FID_MASK) == PSCI_FID_VALUE) 85 86 /******************************************************************************* 87 * PSCI Migrate and friends 88 ******************************************************************************/ 89 #define PSCI_TOS_UP_MIG_CAP 0 90 #define PSCI_TOS_NOT_UP_MIG_CAP 1 91 #define PSCI_TOS_NOT_PRESENT_MP 2 92 93 /******************************************************************************* 94 * PSCI CPU_SUSPEND 'power_state' parameter specific defines 95 ******************************************************************************/ 96 #define PSTATE_ID_SHIFT 0 97 98 #if PSCI_EXTENDED_STATE_ID 99 #define PSTATE_VALID_MASK 0xB0000000 100 #define PSTATE_TYPE_SHIFT 30 101 #define PSTATE_ID_MASK 0xfffffff 102 #else 103 #define PSTATE_VALID_MASK 0xFCFE0000 104 #define PSTATE_TYPE_SHIFT 16 105 #define PSTATE_PWR_LVL_SHIFT 24 106 #define PSTATE_ID_MASK 0xffff 107 #define PSTATE_PWR_LVL_MASK 0x3 108 109 #define psci_get_pstate_pwrlvl(pstate) (((pstate) >> PSTATE_PWR_LVL_SHIFT) & \ 110 PSTATE_PWR_LVL_MASK) 111 #define psci_make_powerstate(state_id, type, pwrlvl) \ 112 (((state_id) & PSTATE_ID_MASK) << PSTATE_ID_SHIFT) |\ 113 (((type) & PSTATE_TYPE_MASK) << PSTATE_TYPE_SHIFT) |\ 114 (((pwrlvl) & PSTATE_PWR_LVL_MASK) << PSTATE_PWR_LVL_SHIFT) 115 #endif /* __PSCI_EXTENDED_STATE_ID__ */ 116 117 #define PSTATE_TYPE_STANDBY 0x0 118 #define PSTATE_TYPE_POWERDOWN 0x1 119 #define PSTATE_TYPE_MASK 0x1 120 121 #define psci_get_pstate_id(pstate) (((pstate) >> PSTATE_ID_SHIFT) & \ 122 PSTATE_ID_MASK) 123 #define psci_get_pstate_type(pstate) (((pstate) >> PSTATE_TYPE_SHIFT) & \ 124 PSTATE_TYPE_MASK) 125 #define psci_check_power_state(pstate) ((pstate) & PSTATE_VALID_MASK) 126 127 /******************************************************************************* 128 * PSCI CPU_FEATURES feature flag specific defines 129 ******************************************************************************/ 130 /* Features flags for CPU SUSPEND power state parameter format. Bits [1:1] */ 131 #define FF_PSTATE_SHIFT 1 132 #define FF_PSTATE_ORIG 0 133 #define FF_PSTATE_EXTENDED 1 134 #if PSCI_EXTENDED_STATE_ID 135 #define FF_PSTATE FF_PSTATE_EXTENDED 136 #else 137 #define FF_PSTATE FF_PSTATE_ORIG 138 #endif 139 140 /* Features flags for CPU SUSPEND OS Initiated mode support. Bits [0:0] */ 141 #define FF_MODE_SUPPORT_SHIFT 0 142 #define FF_SUPPORTS_OS_INIT_MODE 1 143 144 /******************************************************************************* 145 * PSCI version 146 ******************************************************************************/ 147 #define PSCI_MAJOR_VER (1 << 16) 148 #define PSCI_MINOR_VER 0x0 149 150 /******************************************************************************* 151 * PSCI error codes 152 ******************************************************************************/ 153 #define PSCI_E_SUCCESS 0 154 #define PSCI_E_NOT_SUPPORTED -1 155 #define PSCI_E_INVALID_PARAMS -2 156 #define PSCI_E_DENIED -3 157 #define PSCI_E_ALREADY_ON -4 158 #define PSCI_E_ON_PENDING -5 159 #define PSCI_E_INTERN_FAIL -6 160 #define PSCI_E_NOT_PRESENT -7 161 #define PSCI_E_DISABLED -8 162 #define PSCI_E_INVALID_ADDRESS -9 163 164 #define PSCI_INVALID_MPIDR ~((u_register_t)0) 165 166 #ifndef __ASSEMBLY__ 167 168 #include <stdint.h> 169 #include <types.h> 170 171 /* 172 * These are the states reported by the PSCI_AFFINITY_INFO API for the specified 173 * CPU. The definitions of these states can be found in Section 5.7.1 in the 174 * PSCI specification (ARM DEN 0022C). 175 */ 176 typedef enum { 177 AFF_STATE_ON = 0, 178 AFF_STATE_OFF = 1, 179 AFF_STATE_ON_PENDING = 2 180 } aff_info_state_t; 181 182 /* 183 * These are the power states reported by PSCI_NODE_HW_STATE API for the 184 * specified CPU. The definitions of these states can be found in Section 5.15.3 185 * of PSCI specification (ARM DEN 0022C). 186 */ 187 typedef enum { 188 HW_ON = 0, 189 HW_OFF = 1, 190 HW_STANDBY = 2 191 } node_hw_state_t; 192 193 /* 194 * Macro to represent invalid affinity level within PSCI. 195 */ 196 #define PSCI_INVALID_PWR_LVL (PLAT_MAX_PWR_LVL + 1) 197 198 /* 199 * Type for representing the local power state at a particular level. 200 */ 201 typedef uint8_t plat_local_state_t; 202 203 /* The local state macro used to represent RUN state. */ 204 #define PSCI_LOCAL_STATE_RUN 0 205 206 /* 207 * Macro to test whether the plat_local_state is RUN state 208 */ 209 #define is_local_state_run(plat_local_state) \ 210 ((plat_local_state) == PSCI_LOCAL_STATE_RUN) 211 212 /* 213 * Macro to test whether the plat_local_state is RETENTION state 214 */ 215 #define is_local_state_retn(plat_local_state) \ 216 (((plat_local_state) > PSCI_LOCAL_STATE_RUN) && \ 217 ((plat_local_state) <= PLAT_MAX_RET_STATE)) 218 219 /* 220 * Macro to test whether the plat_local_state is OFF state 221 */ 222 #define is_local_state_off(plat_local_state) \ 223 (((plat_local_state) > PLAT_MAX_RET_STATE) && \ 224 ((plat_local_state) <= PLAT_MAX_OFF_STATE)) 225 226 /***************************************************************************** 227 * This data structure defines the representation of the power state parameter 228 * for its exchange between the generic PSCI code and the platform port. For 229 * example, it is used by the platform port to specify the requested power 230 * states during a power management operation. It is used by the generic code to 231 * inform the platform about the target power states that each level should 232 * enter. 233 ****************************************************************************/ 234 typedef struct psci_power_state { 235 /* 236 * The pwr_domain_state[] stores the local power state at each level 237 * for the CPU. 238 */ 239 plat_local_state_t pwr_domain_state[PLAT_MAX_PWR_LVL + 1]; 240 } psci_power_state_t; 241 242 /******************************************************************************* 243 * Structure used to store per-cpu information relevant to the PSCI service. 244 * It is populated in the per-cpu data array. In return we get a guarantee that 245 * this information will not reside on a cache line shared with another cpu. 246 ******************************************************************************/ 247 typedef struct psci_cpu_data { 248 /* State as seen by PSCI Affinity Info API */ 249 aff_info_state_t aff_info_state; 250 251 /* 252 * Highest power level which takes part in a power management 253 * operation. 254 */ 255 unsigned char target_pwrlvl; 256 257 /* The local power state of this CPU */ 258 plat_local_state_t local_state; 259 } psci_cpu_data_t; 260 261 /******************************************************************************* 262 * Structure populated by platform specific code to export routines which 263 * perform common low level power management functions 264 ******************************************************************************/ 265 typedef struct plat_psci_ops { 266 void (*cpu_standby)(plat_local_state_t cpu_state); 267 int (*pwr_domain_on)(u_register_t mpidr); 268 void (*pwr_domain_off)(const psci_power_state_t *target_state); 269 void (*pwr_domain_suspend)(const psci_power_state_t *target_state); 270 void (*pwr_domain_on_finish)(const psci_power_state_t *target_state); 271 void (*pwr_domain_suspend_finish)( 272 const psci_power_state_t *target_state); 273 void (*pwr_domain_pwr_down_wfi)( 274 const psci_power_state_t *target_state) __dead2; 275 void (*system_off)(void) __dead2; 276 void (*system_reset)(void) __dead2; 277 int (*validate_power_state)(unsigned int power_state, 278 psci_power_state_t *req_state); 279 int (*validate_ns_entrypoint)(uintptr_t ns_entrypoint); 280 void (*get_sys_suspend_power_state)( 281 psci_power_state_t *req_state); 282 int (*get_pwr_lvl_state_idx)(plat_local_state_t pwr_domain_state, 283 int pwrlvl); 284 int (*translate_power_state_by_mpidr)(u_register_t mpidr, 285 unsigned int power_state, 286 psci_power_state_t *output_state); 287 int (*get_node_hw_state)(u_register_t mpidr, unsigned int power_level); 288 } plat_psci_ops_t; 289 290 /******************************************************************************* 291 * Function & Data prototypes 292 ******************************************************************************/ 293 unsigned int psci_version(void); 294 int psci_cpu_on(u_register_t target_cpu, 295 uintptr_t entrypoint, 296 u_register_t context_id); 297 int psci_cpu_suspend(unsigned int power_state, 298 uintptr_t entrypoint, 299 u_register_t context_id); 300 int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id); 301 int psci_cpu_off(void); 302 int psci_affinity_info(u_register_t target_affinity, 303 unsigned int lowest_affinity_level); 304 int psci_migrate(u_register_t target_cpu); 305 int psci_migrate_info_type(void); 306 long psci_migrate_info_up_cpu(void); 307 int psci_node_hw_state(u_register_t target_cpu, 308 unsigned int power_level); 309 int psci_features(unsigned int psci_fid); 310 void __dead2 psci_power_down_wfi(void); 311 void psci_arch_setup(void); 312 313 /* 314 * The below API is deprecated. This is now replaced by bl31_warmboot_entry in 315 * AArch64. 316 */ 317 void psci_entrypoint(void) __deprecated; 318 319 #endif /*__ASSEMBLY__*/ 320 321 #endif /* __PSCI_H__ */ 322