1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <arm_def.h> 9 #include <assert.h> 10 #include <bl_common.h> 11 #include <debug.h> 12 #include <desc_image_load.h> 13 #include <generic_delay_timer.h> 14 #ifdef SPD_opteed 15 #include <optee_utils.h> 16 #endif 17 #include <plat_arm.h> 18 #include <platform.h> 19 #include <platform_def.h> 20 #include <string.h> 21 #include <utils.h> 22 23 /* Data structure which holds the extents of the trusted SRAM for BL2 */ 24 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 25 26 /* 27 * Check that BL2_BASE is above ARM_TB_FW_CONFIG_LIMIT. This reserved page is 28 * for `meminfo_t` data structure and fw_configs passed from BL1. 29 */ 30 CASSERT(BL2_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl2_base_overflows); 31 32 /* Weak definitions may be overridden in specific ARM standard platform */ 33 #pragma weak bl2_early_platform_setup2 34 #pragma weak bl2_platform_setup 35 #pragma weak bl2_plat_arch_setup 36 #pragma weak bl2_plat_sec_mem_layout 37 38 #define MAP_BL2_TOTAL MAP_REGION_FLAT( \ 39 bl2_tzram_layout.total_base, \ 40 bl2_tzram_layout.total_size, \ 41 MT_MEMORY | MT_RW | MT_SECURE) 42 43 44 #pragma weak arm_bl2_plat_handle_post_image_load 45 46 /******************************************************************************* 47 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 48 * in x0. This memory layout is sitting at the base of the free trusted SRAM. 49 * Copy it to a safe location before its reclaimed by later BL2 functionality. 50 ******************************************************************************/ 51 void arm_bl2_early_platform_setup(uintptr_t tb_fw_config, 52 struct meminfo *mem_layout) 53 { 54 /* Initialize the console to provide early debug support */ 55 arm_console_boot_init(); 56 57 /* Setup the BL2 memory layout */ 58 bl2_tzram_layout = *mem_layout; 59 60 /* Initialise the IO layer and register platform IO devices */ 61 plat_arm_io_setup(); 62 63 if (tb_fw_config != 0U) 64 arm_bl2_set_tb_cfg_addr((void *)tb_fw_config); 65 } 66 67 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) 68 { 69 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); 70 71 generic_delay_timer_init(); 72 } 73 74 /* 75 * Perform BL2 preload setup. Currently we initialise the dynamic 76 * configuration here. 77 */ 78 void bl2_plat_preload_setup(void) 79 { 80 arm_bl2_dyn_cfg_init(); 81 } 82 83 /* 84 * Perform ARM standard platform setup. 85 */ 86 void arm_bl2_platform_setup(void) 87 { 88 /* Initialize the secure environment */ 89 plat_arm_security_setup(); 90 91 #if defined(PLAT_ARM_MEM_PROT_ADDR) 92 arm_nor_psci_do_static_mem_protect(); 93 #endif 94 } 95 96 void bl2_platform_setup(void) 97 { 98 arm_bl2_platform_setup(); 99 } 100 101 /******************************************************************************* 102 * Perform the very early platform specific architectural setup here. At the 103 * moment this is only initializes the mmu in a quick and dirty way. 104 ******************************************************************************/ 105 void arm_bl2_plat_arch_setup(void) 106 { 107 #if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG 108 /* 109 * Ensure ARM platforms don't use coherent memory in BL2 unless 110 * cryptocell integration is enabled. 111 */ 112 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); 113 #endif 114 115 const mmap_region_t bl_regions[] = { 116 MAP_BL2_TOTAL, 117 ARM_MAP_BL_RO, 118 #if USE_ROMLIB 119 ARM_MAP_ROMLIB_CODE, 120 ARM_MAP_ROMLIB_DATA, 121 #endif 122 #if ARM_CRYPTOCELL_INTEG 123 ARM_MAP_BL_COHERENT_RAM, 124 #endif 125 {0} 126 }; 127 128 setup_page_tables(bl_regions, plat_arm_get_mmap()); 129 130 #ifdef AARCH32 131 enable_mmu_svc_mon(0); 132 #else 133 enable_mmu_el1(0); 134 #endif 135 136 arm_setup_romlib(); 137 } 138 139 void bl2_plat_arch_setup(void) 140 { 141 arm_bl2_plat_arch_setup(); 142 } 143 144 int arm_bl2_handle_post_image_load(unsigned int image_id) 145 { 146 int err = 0; 147 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 148 #ifdef SPD_opteed 149 bl_mem_params_node_t *pager_mem_params = NULL; 150 bl_mem_params_node_t *paged_mem_params = NULL; 151 #endif 152 assert(bl_mem_params); 153 154 switch (image_id) { 155 #ifdef AARCH64 156 case BL32_IMAGE_ID: 157 #ifdef SPD_opteed 158 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 159 assert(pager_mem_params); 160 161 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 162 assert(paged_mem_params); 163 164 err = parse_optee_header(&bl_mem_params->ep_info, 165 &pager_mem_params->image_info, 166 &paged_mem_params->image_info); 167 if (err != 0) { 168 WARN("OPTEE header parse error.\n"); 169 } 170 #endif 171 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry(); 172 break; 173 #endif 174 175 case BL33_IMAGE_ID: 176 /* BL33 expects to receive the primary CPU MPID (through r0) */ 177 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 178 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry(); 179 break; 180 181 #ifdef SCP_BL2_BASE 182 case SCP_BL2_IMAGE_ID: 183 /* The subsequent handling of SCP_BL2 is platform specific */ 184 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info); 185 if (err) { 186 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 187 } 188 break; 189 #endif 190 default: 191 /* Do nothing in default case */ 192 break; 193 } 194 195 return err; 196 } 197 198 /******************************************************************************* 199 * This function can be used by the platforms to update/use image 200 * information for given `image_id`. 201 ******************************************************************************/ 202 int arm_bl2_plat_handle_post_image_load(unsigned int image_id) 203 { 204 return arm_bl2_handle_post_image_load(image_id); 205 } 206 207 int bl2_plat_handle_post_image_load(unsigned int image_id) 208 { 209 return arm_bl2_plat_handle_post_image_load(image_id); 210 } 211