1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __GICV3_PRIVATE_H__ 8 #define __GICV3_PRIVATE_H__ 9 10 #include <gicv3.h> 11 #include <mmio.h> 12 #include <stdint.h> 13 14 /******************************************************************************* 15 * GICv3 private macro definitions 16 ******************************************************************************/ 17 18 /* Constants to indicate the status of the RWP bit */ 19 #define RWP_TRUE 1 20 #define RWP_FALSE 0 21 22 /* 23 * Macro to wait for updates to : 24 * GICD_CTLR[2:0] - the Group Enables 25 * GICD_CTLR[5:4] - the ARE bits 26 * GICD_ICENABLERn - the clearing of enable state for SPIs 27 */ 28 #define gicd_wait_for_pending_write(gicd_base) \ 29 do { \ 30 ; \ 31 } while (gicd_read_ctlr(gicd_base) & GICD_CTLR_RWP_BIT) 32 33 /* 34 * Macro to convert an mpidr to a value suitable for programming into a 35 * GICD_IROUTER. Bits[31:24] in the MPIDR are cleared as they are not relevant 36 * to GICv3. 37 */ 38 #define gicd_irouter_val_from_mpidr(mpidr, irm) \ 39 ((mpidr & ~(0xff << 24)) | \ 40 (irm & IROUTER_IRM_MASK) << IROUTER_IRM_SHIFT) 41 42 /* 43 * Macro to wait for updates to : 44 * GICR_ICENABLER0 45 * GICR_CTLR.DPG1S 46 * GICR_CTLR.DPG1NS 47 * GICR_CTLR.DPG0 48 */ 49 #define gicr_wait_for_pending_write(gicr_base) \ 50 do { \ 51 ; \ 52 } while (gicr_read_ctlr(gicr_base) & GICR_CTLR_RWP_BIT) 53 54 /* 55 * Macro to convert a GICR_TYPER affinity value into a MPIDR value. Bits[31:24] 56 * are zeroes. 57 */ 58 #ifdef AARCH32 59 #define mpidr_from_gicr_typer(typer_val) (((typer_val) >> 32) & 0xffffff) 60 #else 61 #define mpidr_from_gicr_typer(typer_val) \ 62 (((((typer_val) >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) | \ 63 (((typer_val) >> 32) & 0xffffff)) 64 #endif 65 66 /******************************************************************************* 67 * Private GICv3 function prototypes for accessing entire registers. 68 * Note: The raw register values correspond to multiple interrupt IDs and 69 * the number of interrupt IDs involved depends on the register accessed. 70 ******************************************************************************/ 71 unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id); 72 unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id); 73 void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val); 74 void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val); 75 76 /******************************************************************************* 77 * Private GICv3 function prototypes for accessing the GIC registers 78 * corresponding to a single interrupt ID. These functions use bitwise 79 * operations or appropriate register accesses to modify or return 80 * the bit-field corresponding the single interrupt ID. 81 ******************************************************************************/ 82 unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id); 83 unsigned int gicr_get_igrpmodr0(uintptr_t base, unsigned int id); 84 unsigned int gicr_get_igroupr0(uintptr_t base, unsigned int id); 85 void gicd_set_igrpmodr(uintptr_t base, unsigned int id); 86 void gicr_set_igrpmodr0(uintptr_t base, unsigned int id); 87 void gicr_set_isenabler0(uintptr_t base, unsigned int id); 88 void gicr_set_igroupr0(uintptr_t base, unsigned int id); 89 void gicd_clr_igrpmodr(uintptr_t base, unsigned int id); 90 void gicr_clr_igrpmodr0(uintptr_t base, unsigned int id); 91 void gicr_clr_igroupr0(uintptr_t base, unsigned int id); 92 void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri); 93 94 /******************************************************************************* 95 * Private GICv3 helper function prototypes 96 ******************************************************************************/ 97 void gicv3_spis_configure_defaults(uintptr_t gicd_base); 98 void gicv3_ppi_sgi_configure_defaults(uintptr_t gicr_base); 99 void gicv3_secure_spis_configure(uintptr_t gicd_base, 100 unsigned int num_ints, 101 const unsigned int *sec_intr_list, 102 unsigned int int_grp); 103 void gicv3_secure_ppi_sgi_configure(uintptr_t gicr_base, 104 unsigned int num_ints, 105 const unsigned int *sec_intr_list, 106 unsigned int int_grp); 107 void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs, 108 unsigned int rdistif_num, 109 uintptr_t gicr_base, 110 mpidr_hash_fn mpidr_to_core_pos); 111 void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base); 112 void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base); 113 114 /******************************************************************************* 115 * GIC Distributor interface accessors 116 ******************************************************************************/ 117 static inline unsigned int gicd_read_pidr2(uintptr_t base) 118 { 119 return mmio_read_32(base + GICD_PIDR2_GICV3); 120 } 121 122 static inline unsigned long long gicd_read_irouter(uintptr_t base, unsigned int id) 123 { 124 assert(id >= MIN_SPI_ID); 125 return mmio_read_64(base + GICD_IROUTER + (id << 3)); 126 } 127 128 static inline void gicd_write_irouter(uintptr_t base, 129 unsigned int id, 130 unsigned long long affinity) 131 { 132 assert(id >= MIN_SPI_ID); 133 mmio_write_64(base + GICD_IROUTER + (id << 3), affinity); 134 } 135 136 static inline void gicd_clr_ctlr(uintptr_t base, 137 unsigned int bitmap, 138 unsigned int rwp) 139 { 140 gicd_write_ctlr(base, gicd_read_ctlr(base) & ~bitmap); 141 if (rwp) 142 gicd_wait_for_pending_write(base); 143 } 144 145 static inline void gicd_set_ctlr(uintptr_t base, 146 unsigned int bitmap, 147 unsigned int rwp) 148 { 149 gicd_write_ctlr(base, gicd_read_ctlr(base) | bitmap); 150 if (rwp) 151 gicd_wait_for_pending_write(base); 152 } 153 154 /******************************************************************************* 155 * GIC Redistributor interface accessors 156 ******************************************************************************/ 157 static inline unsigned long long gicr_read_ctlr(uintptr_t base) 158 { 159 return mmio_read_64(base + GICR_CTLR); 160 } 161 162 static inline unsigned long long gicr_read_typer(uintptr_t base) 163 { 164 return mmio_read_64(base + GICR_TYPER); 165 } 166 167 static inline unsigned int gicr_read_waker(uintptr_t base) 168 { 169 return mmio_read_32(base + GICR_WAKER); 170 } 171 172 static inline void gicr_write_waker(uintptr_t base, unsigned int val) 173 { 174 mmio_write_32(base + GICR_WAKER, val); 175 } 176 177 /******************************************************************************* 178 * GIC Re-distributor functions for accessing entire registers. 179 * Note: The raw register values correspond to multiple interrupt IDs and 180 * the number of interrupt IDs involved depends on the register accessed. 181 ******************************************************************************/ 182 static inline unsigned int gicr_read_icenabler0(uintptr_t base) 183 { 184 return mmio_read_32(base + GICR_ICENABLER0); 185 } 186 187 static inline void gicr_write_icenabler0(uintptr_t base, unsigned int val) 188 { 189 mmio_write_32(base + GICR_ICENABLER0, val); 190 } 191 192 static inline unsigned int gicr_read_isenabler0(uintptr_t base) 193 { 194 return mmio_read_32(base + GICR_ISENABLER0); 195 } 196 197 static inline void gicr_write_isenabler0(uintptr_t base, unsigned int val) 198 { 199 mmio_write_32(base + GICR_ISENABLER0, val); 200 } 201 202 static inline unsigned int gicr_read_igroupr0(uintptr_t base) 203 { 204 return mmio_read_32(base + GICR_IGROUPR0); 205 } 206 207 static inline void gicr_write_igroupr0(uintptr_t base, unsigned int val) 208 { 209 mmio_write_32(base + GICR_IGROUPR0, val); 210 } 211 212 static inline unsigned int gicr_read_igrpmodr0(uintptr_t base) 213 { 214 return mmio_read_32(base + GICR_IGRPMODR0); 215 } 216 217 static inline void gicr_write_igrpmodr0(uintptr_t base, unsigned int val) 218 { 219 mmio_write_32(base + GICR_IGRPMODR0, val); 220 } 221 222 static inline unsigned int gicr_read_icfgr1(uintptr_t base) 223 { 224 return mmio_read_32(base + GICR_ICFGR1); 225 } 226 227 static inline void gicr_write_icfgr1(uintptr_t base, unsigned int val) 228 { 229 mmio_write_32(base + GICR_ICFGR1, val); 230 } 231 232 #endif /* __GICV3_PRIVATE_H__ */ 233