1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch_helpers.h> 14 #include <common/bl_common.h> 15 #include <common/debug.h> 16 #include <common/tbbr/tbbr_img_def.h> 17 #include <drivers/arm/pl011.h> 18 #include <drivers/arm/pl061_gpio.h> 19 #include <drivers/generic_delay_timer.h> 20 #include <drivers/mmc.h> 21 #include <drivers/synopsys/dw_mmc.h> 22 #include <lib/mmio.h> 23 #include <plat/common/platform.h> 24 25 #include "../../../bl1/bl1_private.h" 26 #include "hi3798cv200.h" 27 #include "plat_private.h" 28 29 /* Data structure which holds the extents of the trusted RAM for BL1 */ 30 static meminfo_t bl1_tzram_layout; 31 static meminfo_t bl2_tzram_layout; 32 static console_pl011_t console; 33 34 /* 35 * Cannot use default weak implementation in bl1_main.c because BL1 RW data is 36 * not at the top of the secure memory. 37 */ 38 int bl1_plat_handle_post_image_load(unsigned int image_id) 39 { 40 image_desc_t *image_desc; 41 entry_point_info_t *ep_info; 42 43 if (image_id != BL2_IMAGE_ID) 44 return 0; 45 46 /* Get the image descriptor */ 47 image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID); 48 assert(image_desc != NULL); 49 50 /* Get the entry point info */ 51 ep_info = &image_desc->ep_info; 52 53 bl2_tzram_layout.total_base = BL2_BASE; 54 bl2_tzram_layout.total_size = BL32_LIMIT - BL2_BASE; 55 56 flush_dcache_range((uintptr_t)&bl2_tzram_layout, sizeof(meminfo_t)); 57 58 ep_info->args.arg1 = (uintptr_t)&bl2_tzram_layout; 59 60 VERBOSE("BL1: BL2 memory layout address = %p\n", 61 (void *)&bl2_tzram_layout); 62 63 return 0; 64 } 65 66 void bl1_early_platform_setup(void) 67 { 68 /* Initialize the console to provide early debug support */ 69 console_pl011_register(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, 70 PL011_BAUDRATE, &console); 71 72 /* Allow BL1 to see the whole Trusted RAM */ 73 bl1_tzram_layout.total_base = BL1_RW_BASE; 74 bl1_tzram_layout.total_size = BL1_RW_SIZE; 75 76 INFO("BL1: 0x%lx - 0x%lx [size = %zu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT, 77 BL1_RAM_LIMIT - BL1_RAM_BASE); 78 } 79 80 void bl1_plat_arch_setup(void) 81 { 82 plat_configure_mmu_el3(bl1_tzram_layout.total_base, 83 bl1_tzram_layout.total_size, 84 BL1_RO_BASE, /* l-loader and BL1 ROM */ 85 BL1_RO_LIMIT, 86 BL_COHERENT_RAM_BASE, 87 BL_COHERENT_RAM_END); 88 } 89 90 void bl1_platform_setup(void) 91 { 92 int i; 93 #if !POPLAR_RECOVERY 94 struct mmc_device_info info; 95 dw_mmc_params_t params = EMMC_INIT_PARAMS(POPLAR_EMMC_DESC_BASE); 96 #endif 97 98 generic_delay_timer_init(); 99 100 pl061_gpio_init(); 101 for (i = 0; i < GPIO_MAX; i++) 102 pl061_gpio_register(GPIO_BASE(i), i); 103 104 #if !POPLAR_RECOVERY 105 /* SoC-specific emmc register are initialized/configured by bootrom */ 106 INFO("BL1: initializing emmc\n"); 107 info.mmc_dev_type = MMC_IS_EMMC; 108 dw_mmc_init(¶ms, &info); 109 #endif 110 111 plat_io_setup(); 112 } 113 114 unsigned int bl1_plat_get_next_image_id(void) 115 { 116 return BL2_IMAGE_ID; 117 } 118