1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <common/bl_common.h> 9 #include <drivers/console.h> 10 #include <lib/xlat_tables/xlat_tables_v2.h> 11 12 #include <tegra_def.h> 13 #include <tegra_private.h> 14 15 /******************************************************************************* 16 * The Tegra power domain tree has a single system level power domain i.e. a 17 * single root node. The first entry in the power domain descriptor specifies 18 * the number of power domains at the highest power level. 19 ******************************************************************************* 20 */ 21 const unsigned char tegra_power_domain_tree_desc[] = { 22 /* No of root nodes */ 23 1, 24 /* No of clusters */ 25 PLATFORM_CLUSTER_COUNT, 26 /* No of CPU cores - cluster0 */ 27 PLATFORM_MAX_CPUS_PER_CLUSTER, 28 /* No of CPU cores - cluster1 */ 29 PLATFORM_MAX_CPUS_PER_CLUSTER 30 }; 31 32 /* sets of MMIO ranges setup */ 33 #define MMIO_RANGE_0_ADDR 0x50000000 34 #define MMIO_RANGE_1_ADDR 0x60000000 35 #define MMIO_RANGE_2_ADDR 0x70000000 36 #define MMIO_RANGE_SIZE 0x200000 37 38 /* 39 * Table of regions to map using the MMU. 40 */ 41 static const mmap_region_t tegra_mmap[] = { 42 MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE, 43 MT_DEVICE | MT_RW | MT_SECURE), 44 MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE, 45 MT_DEVICE | MT_RW | MT_SECURE), 46 MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE, 47 MT_DEVICE | MT_RW | MT_SECURE), 48 {0} 49 }; 50 51 /******************************************************************************* 52 * Set up the pagetables as per the platform memory map & initialize the MMU 53 ******************************************************************************/ 54 const mmap_region_t *plat_get_mmio_map(void) 55 { 56 /* MMIO space */ 57 return tegra_mmap; 58 } 59 60 /******************************************************************************* 61 * Handler to get the System Counter Frequency 62 ******************************************************************************/ 63 unsigned int plat_get_syscnt_freq2(void) 64 { 65 return 19200000; 66 } 67 68 /******************************************************************************* 69 * Maximum supported UART controllers 70 ******************************************************************************/ 71 #define TEGRA210_MAX_UART_PORTS 5 72 73 /******************************************************************************* 74 * This variable holds the UART port base addresses 75 ******************************************************************************/ 76 static uint32_t tegra210_uart_addresses[TEGRA210_MAX_UART_PORTS + 1] = { 77 0, /* undefined - treated as an error case */ 78 TEGRA_UARTA_BASE, 79 TEGRA_UARTB_BASE, 80 TEGRA_UARTC_BASE, 81 TEGRA_UARTD_BASE, 82 TEGRA_UARTE_BASE, 83 }; 84 85 /******************************************************************************* 86 * Retrieve the UART controller base to be used as the console 87 ******************************************************************************/ 88 uint32_t plat_get_console_from_id(int id) 89 { 90 if (id > TEGRA210_MAX_UART_PORTS) 91 return 0; 92 93 return tegra210_uart_addresses[id]; 94 } 95 96 /******************************************************************************* 97 * Initialize the GIC and SGIs 98 ******************************************************************************/ 99 void plat_gic_setup(void) 100 { 101 tegra_gic_setup(NULL, 0); 102 } 103