1/* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <assert_macros.S> 9#include <cortex_a72.h> 10#include <cpu_macros.S> 11#include <debug.h> 12 13 /* --------------------------------------------- 14 * Disable all types of L2 prefetches. 15 * --------------------------------------------- 16 */ 17func cortex_a72_disable_l2_prefetch 18 ldcopr16 r0, r1, CPUECTLR 19 orr64_imm r0, r1, CPUECTLR_DIS_TWD_ACC_PFTCH_BIT 20 bic64_imm r0, r1, (CPUECTLR_L2_IPFTCH_DIST_MASK | \ 21 CPUECTLR_L2_DPFTCH_DIST_MASK) 22 stcopr16 r0, r1, CPUECTLR 23 isb 24 bx lr 25endfunc cortex_a72_disable_l2_prefetch 26 27 /* --------------------------------------------- 28 * Disable the load-store hardware prefetcher. 29 * --------------------------------------------- 30 */ 31func cortex_a72_disable_hw_prefetcher 32 ldcopr16 r0, r1, CPUACTLR 33 orr64_imm r0, r1, CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH 34 stcopr16 r0, r1, CPUACTLR 35 isb 36 dsb ish 37 bx lr 38endfunc cortex_a72_disable_hw_prefetcher 39 40 /* --------------------------------------------- 41 * Disable intra-cluster coherency 42 * Clobbers: r0-r1 43 * --------------------------------------------- 44 */ 45func cortex_a72_disable_smp 46 ldcopr16 r0, r1, CPUECTLR 47 bic64_imm r0, r1, CPUECTLR_SMP_BIT 48 stcopr16 r0, r1, CPUECTLR 49 bx lr 50endfunc cortex_a72_disable_smp 51 52 /* --------------------------------------------- 53 * Disable debug interfaces 54 * --------------------------------------------- 55 */ 56func cortex_a72_disable_ext_debug 57 mov r0, #1 58 stcopr r0, DBGOSDLR 59 isb 60 dsb sy 61 bx lr 62endfunc cortex_a72_disable_ext_debug 63 64 /* ------------------------------------------------- 65 * The CPU Ops reset function for Cortex-A72. 66 * ------------------------------------------------- 67 */ 68func cortex_a72_reset_func 69 /* --------------------------------------------- 70 * Enable the SMP bit. 71 * --------------------------------------------- 72 */ 73 ldcopr16 r0, r1, CPUECTLR 74 orr64_imm r0, r1, CPUECTLR_SMP_BIT 75 stcopr16 r0, r1, CPUECTLR 76 isb 77 bx lr 78endfunc cortex_a72_reset_func 79 80 /* ---------------------------------------------------- 81 * The CPU Ops core power down function for Cortex-A72. 82 * ---------------------------------------------------- 83 */ 84func cortex_a72_core_pwr_dwn 85 push {r12, lr} 86 87 /* Assert if cache is enabled */ 88#if ASM_ASSERTION 89 ldcopr r0, SCTLR 90 tst r0, #SCTLR_C_BIT 91 ASM_ASSERT(eq) 92#endif 93 94 /* --------------------------------------------- 95 * Disable the L2 prefetches. 96 * --------------------------------------------- 97 */ 98 bl cortex_a72_disable_l2_prefetch 99 100 /* --------------------------------------------- 101 * Disable the load-store hardware prefetcher. 102 * --------------------------------------------- 103 */ 104 bl cortex_a72_disable_hw_prefetcher 105 106 /* --------------------------------------------- 107 * Flush L1 caches. 108 * --------------------------------------------- 109 */ 110 mov r0, #DC_OP_CISW 111 bl dcsw_op_level1 112 113 /* --------------------------------------------- 114 * Come out of intra cluster coherency 115 * --------------------------------------------- 116 */ 117 bl cortex_a72_disable_smp 118 119 /* --------------------------------------------- 120 * Force the debug interfaces to be quiescent 121 * --------------------------------------------- 122 */ 123 pop {r12, lr} 124 b cortex_a72_disable_ext_debug 125endfunc cortex_a72_core_pwr_dwn 126 127 /* ------------------------------------------------------- 128 * The CPU Ops cluster power down function for Cortex-A72. 129 * ------------------------------------------------------- 130 */ 131func cortex_a72_cluster_pwr_dwn 132 push {r12, lr} 133 134 /* Assert if cache is enabled */ 135#if ASM_ASSERTION 136 ldcopr r0, SCTLR 137 tst r0, #SCTLR_C_BIT 138 ASM_ASSERT(eq) 139#endif 140 141 /* --------------------------------------------- 142 * Disable the L2 prefetches. 143 * --------------------------------------------- 144 */ 145 bl cortex_a72_disable_l2_prefetch 146 147 /* --------------------------------------------- 148 * Disable the load-store hardware prefetcher. 149 * --------------------------------------------- 150 */ 151 bl cortex_a72_disable_hw_prefetcher 152 153#if !SKIP_A72_L1_FLUSH_PWR_DWN 154 /* --------------------------------------------- 155 * Flush L1 caches. 156 * --------------------------------------------- 157 */ 158 mov r0, #DC_OP_CISW 159 bl dcsw_op_level1 160#endif 161 162 /* --------------------------------------------- 163 * Disable the optional ACP. 164 * --------------------------------------------- 165 */ 166 bl plat_disable_acp 167 168 /* ------------------------------------------------- 169 * Flush the L2 caches. 170 * ------------------------------------------------- 171 */ 172 mov r0, #DC_OP_CISW 173 bl dcsw_op_level2 174 175 /* --------------------------------------------- 176 * Come out of intra cluster coherency 177 * --------------------------------------------- 178 */ 179 bl cortex_a72_disable_smp 180 181 /* --------------------------------------------- 182 * Force the debug interfaces to be quiescent 183 * --------------------------------------------- 184 */ 185 pop {r12, lr} 186 b cortex_a72_disable_ext_debug 187endfunc cortex_a72_cluster_pwr_dwn 188 189declare_cpu_ops cortex_a72, CORTEX_A72_MIDR, \ 190 cortex_a72_reset_func, \ 191 cortex_a72_core_pwr_dwn, \ 192 cortex_a72_cluster_pwr_dwn 193