1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <utils_def.h> 12 #include "../hikey960_def.h" 13 14 /* Special value used to verify platform parameters from BL2 to BL3-1 */ 15 #define HIKEY960_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 16 17 /* 18 * Generic platform constants 19 */ 20 21 /* Size of cacheable stacks */ 22 #define PLATFORM_STACK_SIZE 0x1000 23 24 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 25 26 #define PLATFORM_CACHE_LINE_SIZE 64 27 #define PLATFORM_CLUSTER_COUNT 2 28 #define PLATFORM_CORE_COUNT_PER_CLUSTER 4 29 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 30 PLATFORM_CORE_COUNT_PER_CLUSTER) 31 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 32 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ 33 PLATFORM_CLUSTER_COUNT + 1) 34 35 #define PLAT_MAX_RET_STATE U(1) 36 #define PLAT_MAX_OFF_STATE U(2) 37 38 #define MAX_IO_DEVICES 3 39 #define MAX_IO_HANDLES 4 40 /* UFS RPMB and UFS User Data */ 41 #define MAX_IO_BLOCK_DEVICES 2 42 43 44 /* 45 * Platform memory map related constants 46 */ 47 48 /* 49 * BL1 specific defines. 50 */ 51 #define BL1_RO_BASE (0x1AC00000) 52 #define BL1_RO_LIMIT (BL1_RO_BASE + 0x20000) 53 #define BL1_RW_BASE (BL1_RO_LIMIT) /* 1AC2_0000 */ 54 #define BL1_RW_SIZE (0x00188000) 55 #define BL1_RW_LIMIT (0x1B000000) 56 57 /* 58 * BL2 specific defines. 59 */ 60 #define BL2_BASE (0x1AC00000) 61 #define BL2_LIMIT (BL2_BASE + 0x58000) /* 1AC5_8000 */ 62 63 /* 64 * BL31 specific defines. 65 */ 66 #define BL31_BASE (BL2_LIMIT) /* 1AC5_8000 */ 67 #define BL31_LIMIT (BL31_BASE + 0x40000) /* 1AC9_8000 */ 68 69 /* 70 * BL3-2 specific defines. 71 */ 72 73 /* 74 * The TSP currently executes from TZC secured area of DRAM. 75 */ 76 #define BL32_DRAM_BASE DDR_SEC_BASE 77 #define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE) 78 79 #ifdef SPD_opteed 80 /* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */ 81 #define HIKEY960_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - HIKEY960_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x3FC0_0000 */ 82 #define HIKEY960_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */ 83 #endif 84 85 #if (HIKEY960_TSP_RAM_LOCATION_ID == HIKEY960_DRAM_ID) 86 #define TSP_SEC_MEM_BASE BL32_DRAM_BASE 87 #define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE) 88 #define BL32_BASE BL32_DRAM_BASE 89 #define BL32_LIMIT BL32_DRAM_LIMIT 90 #elif (HIKEY960_TSP_RAM_LOCATION_ID == HIKEY960_SRAM_ID) 91 #error "SRAM storage of TSP payload is currently unsupported" 92 #else 93 #error "Currently unsupported HIKEY960_TSP_LOCATION_ID value" 94 #endif 95 96 /* BL32 is mandatory in AArch32 */ 97 #ifndef AARCH32 98 #ifdef SPD_none 99 #undef BL32_BASE 100 #endif /* SPD_none */ 101 #endif 102 103 #define NS_BL1U_BASE (BL31_LIMIT) /* 1AC9_8000 */ 104 #define NS_BL1U_SIZE (0x00100000) 105 #define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE) 106 107 #define HIKEY960_NS_IMAGE_OFFSET (0x1AC28000) /* offset in l-loader */ 108 #define HIKEY960_NS_TMP_OFFSET (0x1AE00000) 109 110 #define SCP_BL2_BASE (0x89C80000) 111 #define SCP_BL2_SIZE (0x00040000) 112 113 /* 114 * Platform specific page table and MMU setup constants 115 */ 116 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 117 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 118 119 #if defined(IMAGE_BL1) || defined(IMAGE_BL31) || defined(IMAGE_BL32) 120 #define MAX_XLAT_TABLES 3 121 #endif 122 123 #ifdef IMAGE_BL2 124 #ifdef SPD_opteed 125 #define MAX_XLAT_TABLES 4 126 #else 127 #define MAX_XLAT_TABLES 3 128 #endif 129 #endif 130 131 #define MAX_MMAP_REGIONS 16 132 133 /* 134 * Declarations and constants to access the mailboxes safely. Each mailbox is 135 * aligned on the biggest cache line size in the platform. This is known only 136 * to the platform as it might have a combination of integrated and external 137 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 138 * line at any cache level. They could belong to different cpus/clusters & 139 * get written while being protected by different locks causing corruption of 140 * a valid mailbox address. 141 */ 142 #define CACHE_WRITEBACK_SHIFT 6 143 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 144 145 #endif /* PLATFORM_DEF_H */ 146