1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __CSS_DEF_H__ 8 #define __CSS_DEF_H__ 9 10 #include <arm_def.h> 11 #include <tzc400.h> 12 13 /************************************************************************* 14 * Definitions common to all ARM Compute SubSystems (CSS) 15 *************************************************************************/ 16 #define NSROM_BASE 0x1f000000 17 #define NSROM_SIZE 0x00001000 18 19 /* Following covers CSS Peripherals excluding NSROM and NSRAM */ 20 #define CSS_DEVICE_BASE 0x20000000 21 #define CSS_DEVICE_SIZE 0x0e000000 22 23 #define NSRAM_BASE 0x2e000000 24 #define NSRAM_SIZE 0x00008000 25 26 /* System Security Control Registers */ 27 #define SSC_REG_BASE 0x2a420000 28 #define SSC_GPRETN (SSC_REG_BASE + 0x030) 29 30 /* The slave_bootsecure controls access to GPU, DMC and CS. */ 31 #define CSS_NIC400_SLAVE_BOOTSECURE 8 32 33 /* Interrupt handling constants */ 34 #define CSS_IRQ_MHU 69 35 #define CSS_IRQ_GPU_SMMU_0 71 36 #define CSS_IRQ_TZC 80 37 #define CSS_IRQ_TZ_WDOG 86 38 #define CSS_IRQ_SEC_SYS_TIMER 91 39 40 /* 41 * Define a list of Group 1 Secure interrupts as per GICv3 terminology. On a 42 * GICv2 system or mode, the interrupts will be treated as Group 0 interrupts. 43 */ 44 #define CSS_G1S_IRQS CSS_IRQ_MHU, \ 45 CSS_IRQ_GPU_SMMU_0, \ 46 CSS_IRQ_TZC, \ 47 CSS_IRQ_TZ_WDOG, \ 48 CSS_IRQ_SEC_SYS_TIMER 49 50 /* 51 * SCP <=> AP boot configuration 52 * 53 * The SCP/AP boot configuration is a 32-bit word located at a known offset from 54 * the start of the Trusted SRAM. 55 * 56 * Note that the value stored at this address is only valid at boot time, before 57 * the SCP_BL2 image is transferred to SCP. 58 */ 59 #define SCP_BOOT_CFG_ADDR PLAT_CSS_SCP_COM_SHARED_MEM_BASE 60 61 #define CSS_MAP_DEVICE MAP_REGION_FLAT( \ 62 CSS_DEVICE_BASE, \ 63 CSS_DEVICE_SIZE, \ 64 MT_DEVICE | MT_RW | MT_SECURE) 65 66 /* Platform ID address */ 67 #define SSC_VERSION_OFFSET 0x040 68 69 #define SSC_VERSION_CONFIG_SHIFT 28 70 #define SSC_VERSION_MAJOR_REV_SHIFT 24 71 #define SSC_VERSION_MINOR_REV_SHIFT 20 72 #define SSC_VERSION_DESIGNER_ID_SHIFT 12 73 #define SSC_VERSION_PART_NUM_SHIFT 0x0 74 #define SSC_VERSION_CONFIG_MASK 0xf 75 #define SSC_VERSION_MAJOR_REV_MASK 0xf 76 #define SSC_VERSION_MINOR_REV_MASK 0xf 77 #define SSC_VERSION_DESIGNER_ID_MASK 0xff 78 #define SSC_VERSION_PART_NUM_MASK 0xfff 79 80 /* SSC debug configuration registers */ 81 #define SSC_DBGCFG_SET 0x14 82 #define SSC_DBGCFG_CLR 0x18 83 84 #define SPIDEN_INT_CLR_SHIFT 6 85 #define SPIDEN_SEL_SET_SHIFT 7 86 87 #ifndef __ASSEMBLY__ 88 89 /* SSC_VERSION related accessors */ 90 91 /* Returns the part number of the platform */ 92 #define GET_SSC_VERSION_PART_NUM(val) \ 93 (((val) >> SSC_VERSION_PART_NUM_SHIFT) & \ 94 SSC_VERSION_PART_NUM_MASK) 95 96 /* Returns the configuration number of the platform */ 97 #define GET_SSC_VERSION_CONFIG(val) \ 98 (((val) >> SSC_VERSION_CONFIG_SHIFT) & \ 99 SSC_VERSION_CONFIG_MASK) 100 101 #endif /* __ASSEMBLY__ */ 102 103 /************************************************************************* 104 * Required platform porting definitions common to all 105 * ARM Compute SubSystems (CSS) 106 ************************************************************************/ 107 108 /* 109 * The loading of SCP images(SCP_BL2 or SCP_BL2U) is done if there 110 * respective base addresses are defined (i.e SCP_BL2_BASE, SCP_BL2U_BASE). 111 * Hence, `CSS_LOAD_SCP_IMAGES` needs to be set to 1 if BL2 needs to load 112 * an SCP_BL2/SCP_BL2U image. 113 */ 114 #if CSS_LOAD_SCP_IMAGES 115 /* 116 * Load address of SCP_BL2 in CSS platform ports 117 * SCP_BL2 is loaded to the same place as BL31. Once SCP_BL2 is transferred to the 118 * SCP, it is discarded and BL31 is loaded over the top. 119 */ 120 #define SCP_BL2_BASE BL31_BASE 121 #define SCP_BL2_LIMIT (SCP_BL2_BASE + PLAT_CSS_MAX_SCP_BL2_SIZE) 122 123 #define SCP_BL2U_BASE BL31_BASE 124 #define SCP_BL2U_LIMIT (SCP_BL2U_BASE + PLAT_CSS_MAX_SCP_BL2U_SIZE) 125 #endif /* CSS_LOAD_SCP_IMAGES */ 126 127 /* Load address of Non-Secure Image for CSS platform ports */ 128 #define PLAT_ARM_NS_IMAGE_OFFSET 0xE0000000 129 130 /* TZC related constants */ 131 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT_ALL 132 133 /* Trusted mailbox base address common to all CSS */ 134 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 135 136 /* 137 * Parsing of CPU and Cluster states, as returned by 'Get CSS Power State' SCP 138 * command 139 */ 140 #define CSS_CLUSTER_PWR_STATE_ON 0 141 #define CSS_CLUSTER_PWR_STATE_OFF 3 142 143 #define CSS_CPU_PWR_STATE_ON 1 144 #define CSS_CPU_PWR_STATE_OFF 0 145 #define CSS_CPU_PWR_STATE(state, n) (((state) >> (n)) & 1) 146 147 #endif /* __CSS_DEF_H__ */ 148