1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <core_off_arisc.h> 10 #include <debug.h> 11 #include <delay_timer.h> 12 #include <mmio.h> 13 #include <platform.h> 14 #include <platform_def.h> 15 #include <sunxi_cpucfg.h> 16 #include <sunxi_mmap.h> 17 #include <sunxi_private.h> 18 #include <utils_def.h> 19 20 static void sunxi_cpu_disable_power(unsigned int cluster, unsigned int core) 21 { 22 if (mmio_read_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core)) == 0xff) 23 return; 24 25 VERBOSE("PSCI: Disabling power to cluster %d core %d\n", cluster, core); 26 27 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xff); 28 } 29 30 static void sunxi_cpu_enable_power(unsigned int cluster, unsigned int core) 31 { 32 if (mmio_read_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core)) == 0) 33 return; 34 35 VERBOSE("PSCI: Enabling power to cluster %d core %d\n", cluster, core); 36 37 /* Power enable sequence from original Allwinner sources */ 38 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xfe); 39 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xf8); 40 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xe0); 41 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0x80); 42 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0x00); 43 } 44 45 void sunxi_cpu_off(unsigned int cluster, unsigned int core) 46 { 47 int corenr = cluster * PLATFORM_MAX_CPUS_PER_CLUSTER + core; 48 49 VERBOSE("PSCI: Powering off cluster %d core %d\n", cluster, core); 50 51 /* Deassert DBGPWRDUP */ 52 mmio_clrbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core)); 53 54 /* We can't turn ourself off like this, but it works for other cores. */ 55 if (plat_my_core_pos() != corenr) { 56 /* Activate the core output clamps, but not for core 0. */ 57 if (corenr != 0) 58 mmio_setbits_32(SUNXI_POWEROFF_GATING_REG(cluster), 59 BIT(core)); 60 /* Assert CPU power-on reset */ 61 mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core)); 62 /* Remove power from the CPU */ 63 sunxi_cpu_disable_power(cluster, core); 64 65 return; 66 } 67 68 /* Simplifies assembly, all SoCs so far are single cluster anyway. */ 69 assert(cluster == 0); 70 71 /* 72 * If we are supposed to turn ourself off, tell the arisc SCP 73 * to do that work for us. The code expects the core mask to be 74 * patched into the first instruction. 75 */ 76 sunxi_execute_arisc_code(arisc_core_off, sizeof(arisc_core_off), 77 0, BIT_32(core)); 78 } 79 80 void sunxi_cpu_on(unsigned int cluster, unsigned int core) 81 { 82 VERBOSE("PSCI: Powering on cluster %d core %d\n", cluster, core); 83 84 /* Assert CPU core reset */ 85 mmio_clrbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core)); 86 /* Assert CPU power-on reset */ 87 mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core)); 88 /* Set CPU to start in AArch64 mode */ 89 mmio_setbits_32(SUNXI_CPUCFG_CLS_CTRL_REG0(cluster), BIT(24 + core)); 90 /* Apply power to the CPU */ 91 sunxi_cpu_enable_power(cluster, core); 92 /* Release the core output clamps */ 93 mmio_clrbits_32(SUNXI_POWEROFF_GATING_REG(cluster), BIT(core)); 94 /* Deassert CPU power-on reset */ 95 mmio_setbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core)); 96 /* Deassert CPU core reset */ 97 mmio_setbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core)); 98 /* Assert DBGPWRDUP */ 99 mmio_setbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core)); 100 } 101 102 void sunxi_disable_secondary_cpus(unsigned int primary_cpu) 103 { 104 for (unsigned int cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu += 1) { 105 if (cpu == primary_cpu) 106 continue; 107 sunxi_cpu_off(cpu / PLATFORM_MAX_CPUS_PER_CLUSTER, 108 cpu % PLATFORM_MAX_CPUS_PER_CLUSTER); 109 } 110 } 111