1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __GICV2_H__ 8 #define __GICV2_H__ 9 10 /******************************************************************************* 11 * GICv2 miscellaneous definitions 12 ******************************************************************************/ 13 /* Interrupt IDs reported by the HPPIR and IAR registers */ 14 #define PENDING_G1_INTID 1022 15 16 /******************************************************************************* 17 * GICv2 specific Distributor interface register offsets and constants. 18 ******************************************************************************/ 19 #define GICD_ITARGETSR 0x800 20 #define GICD_SGIR 0xF00 21 #define GICD_CPENDSGIR 0xF10 22 #define GICD_SPENDSGIR 0xF20 23 #define GICD_PIDR2_GICV2 0xFE8 24 25 #define ITARGETSR_SHIFT 2 26 #define GIC_TARGET_CPU_MASK 0xff 27 28 #define CPENDSGIR_SHIFT 2 29 #define SPENDSGIR_SHIFT CPENDSGIR_SHIFT 30 31 /******************************************************************************* 32 * GICv2 specific CPU interface register offsets and constants. 33 ******************************************************************************/ 34 /* Physical CPU Interface registers */ 35 #define GICC_CTLR 0x0 36 #define GICC_PMR 0x4 37 #define GICC_BPR 0x8 38 #define GICC_IAR 0xC 39 #define GICC_EOIR 0x10 40 #define GICC_RPR 0x14 41 #define GICC_HPPIR 0x18 42 #define GICC_AHPPIR 0x28 43 #define GICC_IIDR 0xFC 44 #define GICC_DIR 0x1000 45 #define GICC_PRIODROP GICC_EOIR 46 47 /* GICC_CTLR bit definitions */ 48 #define EOI_MODE_NS (1 << 10) 49 #define EOI_MODE_S (1 << 9) 50 #define IRQ_BYP_DIS_GRP1 (1 << 8) 51 #define FIQ_BYP_DIS_GRP1 (1 << 7) 52 #define IRQ_BYP_DIS_GRP0 (1 << 6) 53 #define FIQ_BYP_DIS_GRP0 (1 << 5) 54 #define CBPR (1 << 4) 55 #define FIQ_EN_SHIFT 3 56 #define FIQ_EN_BIT (1 << FIQ_EN_SHIFT) 57 #define ACK_CTL (1 << 2) 58 59 /* GICC_IIDR bit masks and shifts */ 60 #define GICC_IIDR_PID_SHIFT 20 61 #define GICC_IIDR_ARCH_SHIFT 16 62 #define GICC_IIDR_REV_SHIFT 12 63 #define GICC_IIDR_IMP_SHIFT 0 64 65 #define GICC_IIDR_PID_MASK 0xfff 66 #define GICC_IIDR_ARCH_MASK 0xf 67 #define GICC_IIDR_REV_MASK 0xf 68 #define GICC_IIDR_IMP_MASK 0xfff 69 70 /* HYP view virtual CPU Interface registers */ 71 #define GICH_CTL 0x0 72 #define GICH_VTR 0x4 73 #define GICH_ELRSR0 0x30 74 #define GICH_ELRSR1 0x34 75 #define GICH_APR0 0xF0 76 #define GICH_LR_BASE 0x100 77 78 /* Virtual CPU Interface registers */ 79 #define GICV_CTL 0x0 80 #define GICV_PRIMASK 0x4 81 #define GICV_BP 0x8 82 #define GICV_INTACK 0xC 83 #define GICV_EOI 0x10 84 #define GICV_RUNNINGPRI 0x14 85 #define GICV_HIGHESTPEND 0x18 86 #define GICV_DEACTIVATE 0x1000 87 88 /* GICD_CTLR bit definitions */ 89 #define CTLR_ENABLE_G1_SHIFT 1 90 #define CTLR_ENABLE_G1_MASK 0x1 91 #define CTLR_ENABLE_G1_BIT (1 << CTLR_ENABLE_G1_SHIFT) 92 93 /* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */ 94 #define INT_ID_MASK 0x3ff 95 96 #ifndef __ASSEMBLY__ 97 98 #include <stdint.h> 99 100 /******************************************************************************* 101 * This structure describes some of the implementation defined attributes of 102 * the GICv2 IP. It is used by the platform port to specify these attributes 103 * in order to initialize the GICv2 driver. The attributes are described 104 * below. 105 * 106 * 1. The 'gicd_base' field contains the base address of the Distributor 107 * interface programmer's view. 108 * 109 * 2. The 'gicc_base' field contains the base address of the CPU Interface 110 * programmer's view. 111 * 112 * 3. The 'g0_interrupt_array' field is a pointer to an array in which each 113 * entry corresponds to an ID of a Group 0 interrupt. 114 * 115 * 4. The 'g0_interrupt_num' field contains the number of entries in the 116 * 'g0_interrupt_array'. 117 ******************************************************************************/ 118 typedef struct gicv2_driver_data { 119 uintptr_t gicd_base; 120 uintptr_t gicc_base; 121 unsigned int g0_interrupt_num; 122 const unsigned int *g0_interrupt_array; 123 } gicv2_driver_data_t; 124 125 /******************************************************************************* 126 * Function prototypes 127 ******************************************************************************/ 128 void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data); 129 void gicv2_distif_init(void); 130 void gicv2_pcpu_distif_init(void); 131 void gicv2_cpuif_enable(void); 132 void gicv2_cpuif_disable(void); 133 unsigned int gicv2_is_fiq_enabled(void); 134 unsigned int gicv2_get_pending_interrupt_type(void); 135 unsigned int gicv2_get_pending_interrupt_id(void); 136 unsigned int gicv2_acknowledge_interrupt(void); 137 void gicv2_end_of_interrupt(unsigned int id); 138 unsigned int gicv2_get_interrupt_group(unsigned int id); 139 140 #endif /* __ASSEMBLY__ */ 141 #endif /* __GICV2_H__ */ 142