1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MMC_H 8 #define MMC_H 9 10 #include <stdint.h> 11 #include <utils_def.h> 12 13 #define MMC_BLOCK_SIZE U(512) 14 #define MMC_BLOCK_MASK (MMC_BLOCK_SIZE - U(1)) 15 #define MMC_BOOT_CLK_RATE (400 * 1000) 16 17 #define MMC_CMD(_x) U(_x) 18 19 #define MMC_ACMD(_x) U(_x) 20 21 #define OCR_POWERUP BIT(31) 22 #define OCR_HCS BIT(30) 23 #define OCR_BYTE_MODE (U(0) << 29) 24 #define OCR_SECTOR_MODE (U(2) << 29) 25 #define OCR_ACCESS_MODE_MASK (U(3) << 29) 26 #define OCR_3_5_3_6 BIT(23) 27 #define OCR_3_4_3_5 BIT(22) 28 #define OCR_3_3_3_4 BIT(21) 29 #define OCR_3_2_3_3 BIT(20) 30 #define OCR_3_1_3_2 BIT(19) 31 #define OCR_3_0_3_1 BIT(18) 32 #define OCR_2_9_3_0 BIT(17) 33 #define OCR_2_8_2_9 BIT(16) 34 #define OCR_2_7_2_8 BIT(15) 35 #define OCR_VDD_MIN_2V7 GENMASK(23, 15) 36 #define OCR_VDD_MIN_2V0 GENMASK(14, 8) 37 #define OCR_VDD_MIN_1V7 BIT(7) 38 39 #define MMC_RSP_48 BIT(0) 40 #define MMC_RSP_136 BIT(1) /* 136 bit response */ 41 #define MMC_RSP_CRC BIT(2) /* expect valid crc */ 42 #define MMC_RSP_CMD_IDX BIT(3) /* response contains cmd idx */ 43 #define MMC_RSP_BUSY BIT(4) /* device may be busy */ 44 45 /* JEDEC 4.51 chapter 6.12 */ 46 #define MMC_RESPONSE_R1 (MMC_RSP_48 | MMC_RSP_CMD_IDX | MMC_RSP_CRC) 47 #define MMC_RESPONSE_R1B (MMC_RESPONSE_R1 | MMC_RSP_BUSY) 48 #define MMC_RESPONSE_R2 (MMC_RSP_48 | MMC_RSP_136 | MMC_RSP_CRC) 49 #define MMC_RESPONSE_R3 (MMC_RSP_48) 50 #define MMC_RESPONSE_R4 (MMC_RSP_48) 51 #define MMC_RESPONSE_R5 (MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX) 52 #define MMC_RESPONSE_R6 (MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX) 53 #define MMC_RESPONSE_R7 (MMC_RSP_48 | MMC_RSP_CRC | MMC_RSP_CMD_IDX) 54 55 /* Value randomly chosen for eMMC RCA, it should be > 1 */ 56 #define MMC_FIX_RCA 6 57 #define RCA_SHIFT_OFFSET 16 58 59 #define CMD_EXTCSD_PARTITION_CONFIG 179 60 #define CMD_EXTCSD_BUS_WIDTH 183 61 #define CMD_EXTCSD_HS_TIMING 185 62 #define CMD_EXTCSD_SEC_CNT 212 63 64 #define PART_CFG_BOOT_PARTITION1_ENABLE (U(1) << 3) 65 #define PART_CFG_PARTITION1_ACCESS (U(1) << 0) 66 67 /* Values in EXT CSD register */ 68 #define MMC_BUS_WIDTH_1 U(0) 69 #define MMC_BUS_WIDTH_4 U(1) 70 #define MMC_BUS_WIDTH_8 U(2) 71 #define MMC_BUS_WIDTH_DDR_4 U(5) 72 #define MMC_BUS_WIDTH_DDR_8 U(6) 73 #define MMC_BOOT_MODE_BACKWARD (U(0) << 3) 74 #define MMC_BOOT_MODE_HS_TIMING (U(1) << 3) 75 #define MMC_BOOT_MODE_DDR (U(2) << 3) 76 77 #define EXTCSD_SET_CMD (U(0) << 24) 78 #define EXTCSD_SET_BITS (U(1) << 24) 79 #define EXTCSD_CLR_BITS (U(2) << 24) 80 #define EXTCSD_WRITE_BYTES (U(3) << 24) 81 #define EXTCSD_CMD(x) (((x) & 0xff) << 16) 82 #define EXTCSD_VALUE(x) (((x) & 0xff) << 8) 83 #define EXTCSD_CMD_SET_NORMAL U(1) 84 85 #define CSD_TRAN_SPEED_UNIT_MASK GENMASK(2, 0) 86 #define CSD_TRAN_SPEED_MULT_MASK GENMASK(6, 3) 87 #define CSD_TRAN_SPEED_MULT_SHIFT 3 88 89 #define STATUS_CURRENT_STATE(x) (((x) & 0xf) << 9) 90 #define STATUS_READY_FOR_DATA BIT(8) 91 #define STATUS_SWITCH_ERROR BIT(7) 92 #define MMC_GET_STATE(x) (((x) >> 9) & 0xf) 93 #define MMC_STATE_IDLE 0 94 #define MMC_STATE_READY 1 95 #define MMC_STATE_IDENT 2 96 #define MMC_STATE_STBY 3 97 #define MMC_STATE_TRAN 4 98 #define MMC_STATE_DATA 5 99 #define MMC_STATE_RCV 6 100 #define MMC_STATE_PRG 7 101 #define MMC_STATE_DIS 8 102 #define MMC_STATE_BTST 9 103 #define MMC_STATE_SLP 10 104 105 #define MMC_FLAG_CMD23 (U(1) << 0) 106 107 #define CMD8_CHECK_PATTERN U(0xAA) 108 #define VHS_2_7_3_6_V BIT(8) 109 110 #define SD_SCR_BUS_WIDTH_1 BIT(8) 111 #define SD_SCR_BUS_WIDTH_4 BIT(10) 112 113 struct mmc_cmd { 114 unsigned int cmd_idx; 115 unsigned int cmd_arg; 116 unsigned int resp_type; 117 unsigned int resp_data[4]; 118 }; 119 120 struct mmc_ops { 121 void (*init)(void); 122 int (*send_cmd)(struct mmc_cmd *cmd); 123 int (*set_ios)(unsigned int clk, unsigned int width); 124 int (*prepare)(int lba, uintptr_t buf, size_t size); 125 int (*read)(int lba, uintptr_t buf, size_t size); 126 int (*write)(int lba, const uintptr_t buf, size_t size); 127 }; 128 129 struct mmc_csd_emmc { 130 unsigned int not_used: 1; 131 unsigned int crc: 7; 132 unsigned int ecc: 2; 133 unsigned int file_format: 2; 134 unsigned int tmp_write_protect: 1; 135 unsigned int perm_write_protect: 1; 136 unsigned int copy: 1; 137 unsigned int file_format_grp: 1; 138 139 unsigned int reserved_1: 5; 140 unsigned int write_bl_partial: 1; 141 unsigned int write_bl_len: 4; 142 unsigned int r2w_factor: 3; 143 unsigned int default_ecc: 2; 144 unsigned int wp_grp_enable: 1; 145 146 unsigned int wp_grp_size: 5; 147 unsigned int erase_grp_mult: 5; 148 unsigned int erase_grp_size: 5; 149 unsigned int c_size_mult: 3; 150 unsigned int vdd_w_curr_max: 3; 151 unsigned int vdd_w_curr_min: 3; 152 unsigned int vdd_r_curr_max: 3; 153 unsigned int vdd_r_curr_min: 3; 154 unsigned int c_size_low: 2; 155 156 unsigned int c_size_high: 10; 157 unsigned int reserved_2: 2; 158 unsigned int dsr_imp: 1; 159 unsigned int read_blk_misalign: 1; 160 unsigned int write_blk_misalign: 1; 161 unsigned int read_bl_partial: 1; 162 unsigned int read_bl_len: 4; 163 unsigned int ccc: 12; 164 165 unsigned int tran_speed: 8; 166 unsigned int nsac: 8; 167 unsigned int taac: 8; 168 unsigned int reserved_3: 2; 169 unsigned int spec_vers: 4; 170 unsigned int csd_structure: 2; 171 }; 172 173 struct mmc_csd_sd_v2 { 174 unsigned int not_used: 1; 175 unsigned int crc: 7; 176 unsigned int reserved_1: 2; 177 unsigned int file_format: 2; 178 unsigned int tmp_write_protect: 1; 179 unsigned int perm_write_protect: 1; 180 unsigned int copy: 1; 181 unsigned int file_format_grp: 1; 182 183 unsigned int reserved_2: 5; 184 unsigned int write_bl_partial: 1; 185 unsigned int write_bl_len: 4; 186 unsigned int r2w_factor: 3; 187 unsigned int reserved_3: 2; 188 unsigned int wp_grp_enable: 1; 189 190 unsigned int wp_grp_size: 7; 191 unsigned int sector_size: 7; 192 unsigned int erase_block_en: 1; 193 unsigned int reserved_4: 1; 194 unsigned int c_size_low: 16; 195 196 unsigned int c_size_high: 6; 197 unsigned int reserved_5: 6; 198 unsigned int dsr_imp: 1; 199 unsigned int read_blk_misalign: 1; 200 unsigned int write_blk_misalign: 1; 201 unsigned int read_bl_partial: 1; 202 unsigned int read_bl_len: 4; 203 unsigned int ccc: 12; 204 205 unsigned int tran_speed: 8; 206 unsigned int nsac: 8; 207 unsigned int taac: 8; 208 unsigned int reserved_6: 6; 209 unsigned int csd_structure: 2; 210 }; 211 212 enum mmc_device_type { 213 MMC_IS_EMMC, 214 MMC_IS_SD, 215 MMC_IS_SD_HC, 216 }; 217 218 struct mmc_device_info { 219 unsigned long long device_size; /* Size of device in bytes */ 220 unsigned int block_size; /* Block size in bytes */ 221 unsigned int max_bus_freq; /* Max bus freq in Hz */ 222 enum mmc_device_type mmc_dev_type; /* Type of MMC */ 223 }; 224 225 size_t mmc_read_blocks(int lba, uintptr_t buf, size_t size); 226 size_t mmc_write_blocks(int lba, const uintptr_t buf, size_t size); 227 size_t mmc_erase_blocks(int lba, size_t size); 228 size_t mmc_rpmb_read_blocks(int lba, uintptr_t buf, size_t size); 229 size_t mmc_rpmb_write_blocks(int lba, const uintptr_t buf, size_t size); 230 size_t mmc_rpmb_erase_blocks(int lba, size_t size); 231 int mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk, 232 unsigned int width, unsigned int flags, 233 struct mmc_device_info *device_info); 234 235 #endif /* MMC_H */ 236