1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/debug.h> 14 #include <lib/cassert.h> 15 #include <plat/common/platform.h> 16 17 #include <css_pm.h> 18 #include <plat_arm.h> 19 20 #include "../drivers/scp/css_scp.h" 21 22 /* Allow CSS platforms to override `plat_arm_psci_pm_ops` */ 23 #pragma weak plat_arm_psci_pm_ops 24 25 #if ARM_RECOM_STATE_ID_ENC 26 /* 27 * The table storing the valid idle power states. Ensure that the 28 * array entries are populated in ascending order of state-id to 29 * enable us to use binary search during power state validation. 30 * The table must be terminated by a NULL entry. 31 */ 32 const unsigned int arm_pm_idle_states[] = { 33 /* State-id - 0x001 */ 34 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RUN, 35 ARM_LOCAL_STATE_RET, ARM_PWR_LVL0, PSTATE_TYPE_STANDBY), 36 /* State-id - 0x002 */ 37 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RUN, 38 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN), 39 /* State-id - 0x022 */ 40 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF, 41 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN), 42 #if PLAT_MAX_PWR_LVL > ARM_PWR_LVL1 43 /* State-id - 0x222 */ 44 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF, 45 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL2, PSTATE_TYPE_POWERDOWN), 46 #endif 47 0, 48 }; 49 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 50 51 /* 52 * All the power management helpers in this file assume at least cluster power 53 * level is supported. 54 */ 55 CASSERT(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL1, 56 assert_max_pwr_lvl_supported_mismatch); 57 58 /* 59 * Ensure that the PLAT_MAX_PWR_LVL is not greater than CSS_SYSTEM_PWR_DMN_LVL 60 * assumed by the CSS layer. 61 */ 62 CASSERT(PLAT_MAX_PWR_LVL <= CSS_SYSTEM_PWR_DMN_LVL, 63 assert_max_pwr_lvl_higher_than_css_sys_lvl); 64 65 /******************************************************************************* 66 * Handler called when a power domain is about to be turned on. The 67 * level and mpidr determine the affinity instance. 68 ******************************************************************************/ 69 int css_pwr_domain_on(u_register_t mpidr) 70 { 71 css_scp_on(mpidr); 72 73 return PSCI_E_SUCCESS; 74 } 75 76 static void css_pwr_domain_on_finisher_common( 77 const psci_power_state_t *target_state) 78 { 79 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF); 80 81 /* Enable the gic cpu interface */ 82 plat_arm_gic_cpuif_enable(); 83 84 /* 85 * Perform the common cluster specific operations i.e enable coherency 86 * if this cluster was off. 87 */ 88 if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) 89 plat_arm_interconnect_enter_coherency(); 90 } 91 92 /******************************************************************************* 93 * Handler called when a power level has just been powered on after 94 * being turned off earlier. The target_state encodes the low power state that 95 * each level has woken up from. This handler would never be invoked with 96 * the system power domain uninitialized as either the primary would have taken 97 * care of it as part of cold boot or the first core awakened from system 98 * suspend would have already initialized it. 99 ******************************************************************************/ 100 void css_pwr_domain_on_finish(const psci_power_state_t *target_state) 101 { 102 /* Assert that the system power domain need not be initialized */ 103 assert(css_system_pwr_state(target_state) == ARM_LOCAL_STATE_RUN); 104 105 /* Program the gic per-cpu distributor or re-distributor interface */ 106 plat_arm_gic_pcpu_init(); 107 108 css_pwr_domain_on_finisher_common(target_state); 109 } 110 111 /******************************************************************************* 112 * Common function called while turning a cpu off or suspending it. It is called 113 * from css_off() or css_suspend() when these functions in turn are called for 114 * power domain at the highest power level which will be powered down. It 115 * performs the actions common to the OFF and SUSPEND calls. 116 ******************************************************************************/ 117 static void css_power_down_common(const psci_power_state_t *target_state) 118 { 119 /* Prevent interrupts from spuriously waking up this cpu */ 120 plat_arm_gic_cpuif_disable(); 121 122 /* Cluster is to be turned off, so disable coherency */ 123 if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) 124 plat_arm_interconnect_exit_coherency(); 125 } 126 127 /******************************************************************************* 128 * Handler called when a power domain is about to be turned off. The 129 * target_state encodes the power state that each level should transition to. 130 ******************************************************************************/ 131 void css_pwr_domain_off(const psci_power_state_t *target_state) 132 { 133 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF); 134 css_power_down_common(target_state); 135 css_scp_off(target_state); 136 } 137 138 /******************************************************************************* 139 * Handler called when a power domain is about to be suspended. The 140 * target_state encodes the power state that each level should transition to. 141 ******************************************************************************/ 142 void css_pwr_domain_suspend(const psci_power_state_t *target_state) 143 { 144 /* 145 * CSS currently supports retention only at cpu level. Just return 146 * as nothing is to be done for retention. 147 */ 148 if (CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET) 149 return; 150 151 152 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF); 153 css_power_down_common(target_state); 154 155 /* Perform system domain state saving if issuing system suspend */ 156 if (css_system_pwr_state(target_state) == ARM_LOCAL_STATE_OFF) { 157 arm_system_pwr_domain_save(); 158 159 /* Power off the Redistributor after having saved its context */ 160 plat_arm_gic_redistif_off(); 161 } 162 163 css_scp_suspend(target_state); 164 } 165 166 /******************************************************************************* 167 * Handler called when a power domain has just been powered on after 168 * having been suspended earlier. The target_state encodes the low power state 169 * that each level has woken up from. 170 * TODO: At the moment we reuse the on finisher and reinitialize the secure 171 * context. Need to implement a separate suspend finisher. 172 ******************************************************************************/ 173 void css_pwr_domain_suspend_finish( 174 const psci_power_state_t *target_state) 175 { 176 /* Return as nothing is to be done on waking up from retention. */ 177 if (CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET) 178 return; 179 180 /* Perform system domain restore if woken up from system suspend */ 181 if (css_system_pwr_state(target_state) == ARM_LOCAL_STATE_OFF) 182 /* 183 * At this point, the Distributor must be powered on to be ready 184 * to have its state restored. The Redistributor will be powered 185 * on as part of gicv3_rdistif_init_restore. 186 */ 187 arm_system_pwr_domain_resume(); 188 189 css_pwr_domain_on_finisher_common(target_state); 190 } 191 192 /******************************************************************************* 193 * Handlers to shutdown/reboot the system 194 ******************************************************************************/ 195 void __dead2 css_system_off(void) 196 { 197 css_scp_sys_shutdown(); 198 } 199 200 void __dead2 css_system_reset(void) 201 { 202 css_scp_sys_reboot(); 203 } 204 205 /******************************************************************************* 206 * Handler called when the CPU power domain is about to enter standby. 207 ******************************************************************************/ 208 void css_cpu_standby(plat_local_state_t cpu_state) 209 { 210 unsigned int scr; 211 212 assert(cpu_state == ARM_LOCAL_STATE_RET); 213 214 scr = read_scr_el3(); 215 /* 216 * Enable the Non secure interrupt to wake the CPU. 217 * In GICv3 affinity routing mode, the non secure group1 interrupts use 218 * the PhysicalFIQ at EL3 whereas in GICv2, it uses the PhysicalIRQ. 219 * Enabling both the bits works for both GICv2 mode and GICv3 affinity 220 * routing mode. 221 */ 222 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); 223 isb(); 224 dsb(); 225 wfi(); 226 227 /* 228 * Restore SCR to the original value, synchronisation of scr_el3 is 229 * done by eret while el3_exit to save some execution cycles. 230 */ 231 write_scr_el3(scr); 232 } 233 234 /******************************************************************************* 235 * Handler called to return the 'req_state' for system suspend. 236 ******************************************************************************/ 237 void css_get_sys_suspend_power_state(psci_power_state_t *req_state) 238 { 239 unsigned int i; 240 241 /* 242 * System Suspend is supported only if the system power domain node 243 * is implemented. 244 */ 245 assert(PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL); 246 247 for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++) 248 req_state->pwr_domain_state[i] = ARM_LOCAL_STATE_OFF; 249 } 250 251 /******************************************************************************* 252 * Handler to query CPU/cluster power states from SCP 253 ******************************************************************************/ 254 int css_node_hw_state(u_register_t mpidr, unsigned int power_level) 255 { 256 return css_scp_get_power_state(mpidr, power_level); 257 } 258 259 /* 260 * The system power domain suspend is only supported only via 261 * PSCI SYSTEM_SUSPEND API. PSCI CPU_SUSPEND request to system power domain 262 * will be downgraded to the lower level. 263 */ 264 static int css_validate_power_state(unsigned int power_state, 265 psci_power_state_t *req_state) 266 { 267 int rc; 268 rc = arm_validate_power_state(power_state, req_state); 269 270 /* 271 * Ensure that we don't overrun the pwr_domain_state array in the case 272 * where the platform supported max power level is less than the system 273 * power level 274 */ 275 276 #if (PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL) 277 278 /* 279 * Ensure that the system power domain level is never suspended 280 * via PSCI CPU SUSPEND API. Currently system suspend is only 281 * supported via PSCI SYSTEM SUSPEND API. 282 */ 283 284 req_state->pwr_domain_state[CSS_SYSTEM_PWR_DMN_LVL] = 285 ARM_LOCAL_STATE_RUN; 286 #endif 287 288 return rc; 289 } 290 291 /* 292 * Custom `translate_power_state_by_mpidr` handler for CSS. Unlike in the 293 * `css_validate_power_state`, we do not downgrade the system power 294 * domain level request in `power_state` as it will be used to query the 295 * PSCI_STAT_COUNT/RESIDENCY at the system power domain level. 296 */ 297 static int css_translate_power_state_by_mpidr(u_register_t mpidr, 298 unsigned int power_state, 299 psci_power_state_t *output_state) 300 { 301 return arm_validate_power_state(power_state, output_state); 302 } 303 304 /******************************************************************************* 305 * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard 306 * platform will take care of registering the handlers with PSCI. 307 ******************************************************************************/ 308 plat_psci_ops_t plat_arm_psci_pm_ops = { 309 .pwr_domain_on = css_pwr_domain_on, 310 .pwr_domain_on_finish = css_pwr_domain_on_finish, 311 .pwr_domain_off = css_pwr_domain_off, 312 .cpu_standby = css_cpu_standby, 313 .pwr_domain_suspend = css_pwr_domain_suspend, 314 .pwr_domain_suspend_finish = css_pwr_domain_suspend_finish, 315 .system_off = css_system_off, 316 .system_reset = css_system_reset, 317 .validate_power_state = css_validate_power_state, 318 .validate_ns_entrypoint = arm_validate_psci_entrypoint, 319 .translate_power_state_by_mpidr = css_translate_power_state_by_mpidr, 320 .get_node_hw_state = css_node_hw_state, 321 .get_sys_suspend_power_state = css_get_sys_suspend_power_state, 322 323 #if defined(PLAT_ARM_MEM_PROT_ADDR) 324 .mem_protect_chk = arm_psci_mem_protect_chk, 325 .read_mem_protect = arm_psci_read_mem_protect, 326 .write_mem_protect = arm_nor_psci_write_mem_protect, 327 #endif 328 #if CSS_USE_SCMI_SDS_DRIVER 329 .system_reset2 = css_system_reset2, 330 #endif 331 }; 332