1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <assert.h> 7 #include <gic_common.h> 8 #include <gicv2.h> 9 #include <interrupt_mgmt.h> 10 #include <platform.h> 11 #include <stdbool.h> 12 13 /* 14 * The following platform GIC functions are weakly defined. They 15 * provide typical implementations that may be re-used by multiple 16 * platforms but may also be overridden by a platform if required. 17 */ 18 #pragma weak plat_ic_get_pending_interrupt_id 19 #pragma weak plat_ic_get_pending_interrupt_type 20 #pragma weak plat_ic_acknowledge_interrupt 21 #pragma weak plat_ic_get_interrupt_type 22 #pragma weak plat_ic_end_of_interrupt 23 #pragma weak plat_interrupt_type_to_line 24 25 #pragma weak plat_ic_get_running_priority 26 #pragma weak plat_ic_is_spi 27 #pragma weak plat_ic_is_ppi 28 #pragma weak plat_ic_is_sgi 29 #pragma weak plat_ic_get_interrupt_active 30 #pragma weak plat_ic_enable_interrupt 31 #pragma weak plat_ic_disable_interrupt 32 #pragma weak plat_ic_set_interrupt_priority 33 #pragma weak plat_ic_set_interrupt_type 34 #pragma weak plat_ic_raise_el3_sgi 35 #pragma weak plat_ic_set_spi_routing 36 37 /* 38 * This function returns the highest priority pending interrupt at 39 * the Interrupt controller 40 */ 41 uint32_t plat_ic_get_pending_interrupt_id(void) 42 { 43 unsigned int id; 44 45 id = gicv2_get_pending_interrupt_id(); 46 if (id == GIC_SPURIOUS_INTERRUPT) 47 return INTR_ID_UNAVAILABLE; 48 49 return id; 50 } 51 52 /* 53 * This function returns the type of the highest priority pending interrupt 54 * at the Interrupt controller. In the case of GICv2, the Highest Priority 55 * Pending interrupt register (`GICC_HPPIR`) is read to determine the id of 56 * the pending interrupt. The type of interrupt depends upon the id value 57 * as follows. 58 * 1. id < PENDING_G1_INTID (1022) is reported as a S-EL1 interrupt 59 * 2. id = PENDING_G1_INTID (1022) is reported as a Non-secure interrupt. 60 * 3. id = GIC_SPURIOUS_INTERRUPT (1023) is reported as an invalid interrupt 61 * type. 62 */ 63 uint32_t plat_ic_get_pending_interrupt_type(void) 64 { 65 unsigned int id; 66 67 id = gicv2_get_pending_interrupt_type(); 68 69 /* Assume that all secure interrupts are S-EL1 interrupts */ 70 if (id < PENDING_G1_INTID) { 71 #if GICV2_G0_FOR_EL3 72 return INTR_TYPE_EL3; 73 #else 74 return INTR_TYPE_S_EL1; 75 #endif 76 } 77 78 if (id == GIC_SPURIOUS_INTERRUPT) 79 return INTR_TYPE_INVAL; 80 81 return INTR_TYPE_NS; 82 } 83 84 /* 85 * This function returns the highest priority pending interrupt at 86 * the Interrupt controller and indicates to the Interrupt controller 87 * that the interrupt processing has started. 88 */ 89 uint32_t plat_ic_acknowledge_interrupt(void) 90 { 91 return gicv2_acknowledge_interrupt(); 92 } 93 94 /* 95 * This function returns the type of the interrupt `id`, depending on how 96 * the interrupt has been configured in the interrupt controller 97 */ 98 uint32_t plat_ic_get_interrupt_type(uint32_t id) 99 { 100 unsigned int type; 101 102 type = gicv2_get_interrupt_group(id); 103 104 /* Assume that all secure interrupts are S-EL1 interrupts */ 105 return (type == GICV2_INTR_GROUP1) ? INTR_TYPE_NS : 106 #if GICV2_G0_FOR_EL3 107 INTR_TYPE_EL3; 108 #else 109 INTR_TYPE_S_EL1; 110 #endif 111 } 112 113 /* 114 * This functions is used to indicate to the interrupt controller that 115 * the processing of the interrupt corresponding to the `id` has 116 * finished. 117 */ 118 void plat_ic_end_of_interrupt(uint32_t id) 119 { 120 gicv2_end_of_interrupt(id); 121 } 122 123 /* 124 * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins. 125 * The interrupt controller knows which pin/line it uses to signal a type of 126 * interrupt. It lets the interrupt management framework determine 127 * for a type of interrupt and security state, which line should be used in the 128 * SCR_EL3 to control its routing to EL3. The interrupt line is represented 129 * as the bit position of the IRQ or FIQ bit in the SCR_EL3. 130 */ 131 uint32_t plat_interrupt_type_to_line(uint32_t type, 132 uint32_t security_state) 133 { 134 assert((type == INTR_TYPE_S_EL1) || (type == INTR_TYPE_EL3) || 135 (type == INTR_TYPE_NS)); 136 137 assert(sec_state_is_valid(security_state)); 138 139 /* Non-secure interrupts are signaled on the IRQ line always */ 140 if (type == INTR_TYPE_NS) 141 return __builtin_ctz(SCR_IRQ_BIT); 142 143 /* 144 * Secure interrupts are signaled using the IRQ line if the FIQ is 145 * not enabled else they are signaled using the FIQ line. 146 */ 147 return ((gicv2_is_fiq_enabled() != 0U) ? __builtin_ctz(SCR_FIQ_BIT) : 148 __builtin_ctz(SCR_IRQ_BIT)); 149 } 150 151 unsigned int plat_ic_get_running_priority(void) 152 { 153 return gicv2_get_running_priority(); 154 } 155 156 int plat_ic_is_spi(unsigned int id) 157 { 158 return (id >= MIN_SPI_ID) && (id <= MAX_SPI_ID); 159 } 160 161 int plat_ic_is_ppi(unsigned int id) 162 { 163 return (id >= MIN_PPI_ID) && (id < MIN_SPI_ID); 164 } 165 166 int plat_ic_is_sgi(unsigned int id) 167 { 168 return (id >= MIN_SGI_ID) && (id < MIN_PPI_ID); 169 } 170 171 unsigned int plat_ic_get_interrupt_active(unsigned int id) 172 { 173 return gicv2_get_interrupt_active(id); 174 } 175 176 void plat_ic_enable_interrupt(unsigned int id) 177 { 178 gicv2_enable_interrupt(id); 179 } 180 181 void plat_ic_disable_interrupt(unsigned int id) 182 { 183 gicv2_disable_interrupt(id); 184 } 185 186 void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority) 187 { 188 gicv2_set_interrupt_priority(id, priority); 189 } 190 191 int plat_ic_has_interrupt_type(unsigned int type) 192 { 193 int has_interrupt_type = 0; 194 195 switch (type) { 196 #if GICV2_G0_FOR_EL3 197 case INTR_TYPE_EL3: 198 #else 199 case INTR_TYPE_S_EL1: 200 #endif 201 case INTR_TYPE_NS: 202 has_interrupt_type = 1; 203 break; 204 default: 205 /* Do nothing in default case */ 206 break; 207 } 208 209 return has_interrupt_type; 210 } 211 212 void plat_ic_set_interrupt_type(unsigned int id, unsigned int type) 213 { 214 unsigned int gicv2_type = 0U; 215 216 /* Map canonical interrupt type to GICv2 type */ 217 switch (type) { 218 #if GICV2_G0_FOR_EL3 219 case INTR_TYPE_EL3: 220 #else 221 case INTR_TYPE_S_EL1: 222 #endif 223 gicv2_type = GICV2_INTR_GROUP0; 224 break; 225 case INTR_TYPE_NS: 226 gicv2_type = GICV2_INTR_GROUP1; 227 break; 228 default: 229 assert(0); /* Unreachable */ 230 break; 231 } 232 233 gicv2_set_interrupt_type(id, gicv2_type); 234 } 235 236 void plat_ic_raise_el3_sgi(int sgi_num, u_register_t target) 237 { 238 #if GICV2_G0_FOR_EL3 239 int id; 240 241 /* Target must be a valid MPIDR in the system */ 242 id = plat_core_pos_by_mpidr(target); 243 assert(id >= 0); 244 245 /* Verify that this is a secure SGI */ 246 assert(plat_ic_get_interrupt_type(sgi_num) == INTR_TYPE_EL3); 247 248 gicv2_raise_sgi(sgi_num, id); 249 #else 250 assert(false); 251 #endif 252 } 253 254 void plat_ic_set_spi_routing(unsigned int id, unsigned int routing_mode, 255 u_register_t mpidr) 256 { 257 int proc_num = 0; 258 259 switch (routing_mode) { 260 case INTR_ROUTING_MODE_PE: 261 proc_num = plat_core_pos_by_mpidr(mpidr); 262 assert(proc_num >= 0); 263 break; 264 case INTR_ROUTING_MODE_ANY: 265 /* Bit mask selecting all 8 CPUs as candidates */ 266 proc_num = -1; 267 break; 268 default: 269 assert(0); /* Unreachable */ 270 break; 271 } 272 273 gicv2_set_spi_routing(id, proc_num); 274 } 275 276 void plat_ic_set_interrupt_pending(unsigned int id) 277 { 278 gicv2_set_interrupt_pending(id); 279 } 280 281 void plat_ic_clear_interrupt_pending(unsigned int id) 282 { 283 gicv2_clear_interrupt_pending(id); 284 } 285 286 unsigned int plat_ic_set_priority_mask(unsigned int mask) 287 { 288 return gicv2_set_pmr(mask); 289 } 290 291 unsigned int plat_ic_get_interrupt_id(unsigned int raw) 292 { 293 unsigned int id = (raw & INT_ID_MASK); 294 295 if (id == GIC_SPURIOUS_INTERRUPT) 296 id = INTR_ID_UNAVAILABLE; 297 298 return id; 299 } 300