1 /* 2 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <gic_common.h> 11 #include <interrupt_props.h> 12 #include <utils_def.h> 13 #include "mt8173_def.h" 14 15 /******************************************************************************* 16 * Platform binary types for linking 17 ******************************************************************************/ 18 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 19 #define PLATFORM_LINKER_ARCH aarch64 20 21 /******************************************************************************* 22 * Generic platform constants 23 ******************************************************************************/ 24 25 /* Size of cacheable stacks */ 26 #if defined(IMAGE_BL1) 27 #define PLATFORM_STACK_SIZE 0x440 28 #elif defined(IMAGE_BL2) 29 #define PLATFORM_STACK_SIZE 0x400 30 #elif defined(IMAGE_BL31) 31 #define PLATFORM_STACK_SIZE 0x800 32 #elif defined(IMAGE_BL32) 33 #define PLATFORM_STACK_SIZE 0x440 34 #endif 35 36 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 37 38 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 39 #define PLAT_MAX_PWR_LVL U(2) 40 #define PLAT_MAX_RET_STATE U(1) 41 #define PLAT_MAX_OFF_STATE U(2) 42 #define PLATFORM_SYSTEM_COUNT 1 43 #define PLATFORM_CLUSTER_COUNT 2 44 #define PLATFORM_CLUSTER0_CORE_COUNT 4 45 #define PLATFORM_CLUSTER1_CORE_COUNT 2 46 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 47 PLATFORM_CLUSTER0_CORE_COUNT) 48 #define PLATFORM_MAX_CPUS_PER_CLUSTER 4 49 #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ 50 PLATFORM_CLUSTER_COUNT + \ 51 PLATFORM_CORE_COUNT) 52 53 /******************************************************************************* 54 * Platform memory map related constants 55 ******************************************************************************/ 56 /* 57 * MT8173 SRAM memory layout 58 * 0x100000 +-------------------+ 59 * | shared mem (4KB) | 60 * 0x101000 +-------------------+ 61 * | | 62 * | BL3-1 (124KB) | 63 * | | 64 * 0x120000 +-------------------+ 65 * | reserved (64KB) | 66 * 0x130000 +-------------------+ 67 */ 68 /* TF txet, ro, rw, xlat table, coherent memory ... etc. 69 * Size: release: 128KB, debug: 128KB 70 */ 71 #define TZRAM_BASE (0x100000) 72 #if DEBUG 73 #define TZRAM_SIZE (0x20000) 74 #else 75 #define TZRAM_SIZE (0x20000) 76 #endif 77 78 /* Reserved: 64KB */ 79 #define TZRAM2_BASE (TZRAM_BASE + TZRAM_SIZE) 80 #define TZRAM2_SIZE (0x10000) 81 82 /******************************************************************************* 83 * BL31 specific defines. 84 ******************************************************************************/ 85 /* 86 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 87 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 88 * little space for growth. 89 */ 90 #define BL31_BASE (TZRAM_BASE + 0x1000) 91 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 92 #define TZRAM2_LIMIT (TZRAM2_BASE + TZRAM2_SIZE) 93 94 /******************************************************************************* 95 * Platform specific page table and MMU setup constants 96 ******************************************************************************/ 97 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 98 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 99 #define MAX_XLAT_TABLES 4 100 #define MAX_MMAP_REGIONS 16 101 102 /******************************************************************************* 103 * Declarations and constants to access the mailboxes safely. Each mailbox is 104 * aligned on the biggest cache line size in the platform. This is known only 105 * to the platform as it might have a combination of integrated and external 106 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 107 * line at any cache level. They could belong to different cpus/clusters & 108 * get written while being protected by different locks causing corruption of 109 * a valid mailbox address. 110 ******************************************************************************/ 111 #define CACHE_WRITEBACK_SHIFT 6 112 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 113 114 115 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 116 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 117 118 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 119 INTR_PROP_DESC(MT_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ 120 GIC_INTR_CFG_EDGE), \ 121 INTR_PROP_DESC(MT_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 122 GIC_INTR_CFG_EDGE), \ 123 INTR_PROP_DESC(MT_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ 124 GIC_INTR_CFG_EDGE), \ 125 INTR_PROP_DESC(MT_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ 126 GIC_INTR_CFG_EDGE), \ 127 INTR_PROP_DESC(MT_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ 128 GIC_INTR_CFG_EDGE), \ 129 INTR_PROP_DESC(MT_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ 130 GIC_INTR_CFG_EDGE), \ 131 INTR_PROP_DESC(MT_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ 132 GIC_INTR_CFG_EDGE), \ 133 INTR_PROP_DESC(MT_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ 134 GIC_INTR_CFG_EDGE) 135 136 #define PLAT_ARM_G0_IRQ_PROPS(grp) 137 138 #endif /* PLATFORM_DEF_H */ 139