1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <platform_def.h> 10 #include <assert.h> 11 #include <bl_common.h> 12 #include <pl011.h> 13 #include <debug.h> 14 #include <mmio.h> 15 #include <sq_common.h> 16 17 static console_pl011_t console; 18 static entry_point_info_t bl32_image_ep_info; 19 static entry_point_info_t bl33_image_ep_info; 20 21 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 22 { 23 assert(sec_state_is_valid(type)); 24 return type == NON_SECURE ? &bl33_image_ep_info : &bl32_image_ep_info; 25 } 26 27 /******************************************************************************* 28 * Gets SPSR for BL32 entry 29 ******************************************************************************/ 30 uint32_t sq_get_spsr_for_bl32_entry(void) 31 { 32 /* 33 * The Secure Payload Dispatcher service is responsible for 34 * setting the SPSR prior to entry into the BL32 image. 35 */ 36 return 0; 37 } 38 39 /******************************************************************************* 40 * Gets SPSR for BL33 entry 41 ******************************************************************************/ 42 uint32_t sq_get_spsr_for_bl33_entry(void) 43 { 44 unsigned long el_status; 45 unsigned int mode; 46 uint32_t spsr; 47 48 /* Figure out what mode we enter the non-secure world in */ 49 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 50 el_status &= ID_AA64PFR0_ELX_MASK; 51 52 mode = (el_status) ? MODE_EL2 : MODE_EL1; 53 54 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 55 return spsr; 56 } 57 58 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 59 u_register_t arg2, u_register_t arg3) 60 { 61 /* Initialize the console to provide early debug support */ 62 (void)console_pl011_register(PLAT_SQ_BOOT_UART_BASE, 63 PLAT_SQ_BOOT_UART_CLK_IN_HZ, 64 SQ_CONSOLE_BAUDRATE, &console); 65 66 console_set_scope(&console.console, CONSOLE_FLAG_BOOT | 67 CONSOLE_FLAG_RUNTIME); 68 69 /* There are no parameters from BL2 if BL31 is a reset vector */ 70 assert(arg0 == 0U); 71 assert(arg1 == 0U); 72 73 /* Initialize power controller before setting up topology */ 74 plat_sq_pwrc_setup(); 75 76 #ifdef BL32_BASE 77 struct draminfo di = {0}; 78 79 scpi_get_draminfo(&di); 80 81 /* 82 * Check if OP-TEE has been loaded in Secure RAM allocated 83 * from DRAM1 region 84 */ 85 if ((di.base1 + di.size1) <= BL32_BASE) { 86 NOTICE("OP-TEE has been loaded by SCP firmware\n"); 87 /* Populate entry point information for BL32 */ 88 SET_PARAM_HEAD(&bl32_image_ep_info, 89 PARAM_EP, 90 VERSION_1, 91 0); 92 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 93 bl32_image_ep_info.pc = BL32_BASE; 94 bl32_image_ep_info.spsr = sq_get_spsr_for_bl32_entry(); 95 } else { 96 NOTICE("OP-TEE has not been loaded by SCP firmware\n"); 97 } 98 #endif /* BL32_BASE */ 99 100 /* Populate entry point information for BL33 */ 101 SET_PARAM_HEAD(&bl33_image_ep_info, 102 PARAM_EP, 103 VERSION_1, 104 0); 105 /* 106 * Tell BL31 where the non-trusted software image 107 * is located and the entry state information 108 */ 109 bl33_image_ep_info.pc = PRELOADED_BL33_BASE; 110 bl33_image_ep_info.spsr = sq_get_spsr_for_bl33_entry(); 111 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 112 } 113 114 static void sq_configure_sys_timer(void) 115 { 116 unsigned int reg_val; 117 118 reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); 119 reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); 120 reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); 121 mmio_write_32(SQ_SYS_TIMCTL_BASE + 122 CNTACR_BASE(PLAT_SQ_NSTIMER_FRAME_ID), reg_val); 123 124 reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_SQ_NSTIMER_FRAME_ID)); 125 mmio_write_32(SQ_SYS_TIMCTL_BASE + CNTNSAR, reg_val); 126 } 127 128 void bl31_platform_setup(void) 129 { 130 /* Initialize the CCN interconnect */ 131 plat_sq_interconnect_init(); 132 plat_sq_interconnect_enter_coherency(); 133 134 /* Initialize the GIC driver, cpu and distributor interfaces */ 135 sq_gic_driver_init(); 136 sq_gic_init(); 137 138 /* Enable and initialize the System level generic timer */ 139 mmio_write_32(SQ_SYS_CNTCTL_BASE + CNTCR_OFF, 140 CNTCR_FCREQ(0U) | CNTCR_EN); 141 142 /* Allow access to the System counter timer module */ 143 sq_configure_sys_timer(); 144 } 145 146 void bl31_plat_runtime_setup(void) 147 { 148 struct draminfo *di = (struct draminfo *)(unsigned long)DRAMINFO_BASE; 149 150 scpi_get_draminfo(di); 151 } 152 153 void bl31_plat_arch_setup(void) 154 { 155 sq_mmap_setup(BL31_BASE, BL31_SIZE, NULL); 156 enable_mmu_el3(XLAT_TABLE_NC); 157 } 158 159 void bl31_plat_enable_mmu(uint32_t flags) 160 { 161 enable_mmu_el3(flags | XLAT_TABLE_NC); 162 } 163 164 unsigned int plat_get_syscnt_freq2(void) 165 { 166 unsigned int counter_base_frequency; 167 168 /* Read the frequency from Frequency modes table */ 169 counter_base_frequency = mmio_read_32(SQ_SYS_CNTCTL_BASE + CNTFID_OFF); 170 171 /* The first entry of the frequency modes table must not be 0 */ 172 if (counter_base_frequency == 0) 173 panic(); 174 175 return counter_base_frequency; 176 } 177