1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef ARM_SPM_DEF_H 7 #define ARM_SPM_DEF_H 8 9 #include <lib/utils_def.h> 10 #include <lib/xlat_tables/xlat_tables_defs.h> 11 12 #include <arm_def.h> 13 14 /* 15 * Reserve 4 MiB for binaries of Secure Partitions and Resource Description 16 * blobs. 17 */ 18 #define PLAT_SP_PACKAGE_BASE BL32_BASE 19 #define PLAT_SP_PACKAGE_SIZE ULL(0x400000) 20 21 #define PLAT_MAP_SP_PACKAGE_MEM_RO MAP_REGION_FLAT( \ 22 PLAT_SP_PACKAGE_BASE, \ 23 PLAT_SP_PACKAGE_SIZE, \ 24 MT_MEMORY | MT_RO | MT_SECURE) 25 #define PLAT_MAP_SP_PACKAGE_MEM_RW MAP_REGION_FLAT( \ 26 PLAT_SP_PACKAGE_BASE, \ 27 PLAT_SP_PACKAGE_SIZE, \ 28 MT_MEMORY | MT_RW | MT_SECURE) 29 30 /* 31 * The rest of the memory reserved for BL32 is free for SPM to use it as memory 32 * pool to allocate memory regions requested in the resource description. 33 */ 34 #define PLAT_SPM_HEAP_BASE (PLAT_SP_PACKAGE_BASE + PLAT_SP_PACKAGE_SIZE) 35 #define PLAT_SPM_HEAP_SIZE (BL32_LIMIT - BL32_BASE - PLAT_SP_PACKAGE_SIZE) 36 37 #if SPM_DEPRECATED 38 39 /* 40 * If BL31 is placed in DRAM, place the Secure Partition in DRAM right after the 41 * region used by BL31. If BL31 it is placed in SRAM, put the Secure Partition 42 * at the base of DRAM. 43 */ 44 #define ARM_SP_IMAGE_BASE BL32_BASE 45 #define ARM_SP_IMAGE_LIMIT BL32_LIMIT 46 /* The maximum size of the S-EL0 payload can be 3MB */ 47 #define ARM_SP_IMAGE_SIZE ULL(0x300000) 48 49 #ifdef IMAGE_BL2 50 /* SPM Payload memory. Mapped as RW in BL2. */ 51 #define ARM_SP_IMAGE_MMAP MAP_REGION_FLAT( \ 52 ARM_SP_IMAGE_BASE, \ 53 ARM_SP_IMAGE_SIZE, \ 54 MT_MEMORY | MT_RW | MT_SECURE) 55 #endif 56 57 #ifdef IMAGE_BL31 58 /* SPM Payload memory. Mapped as code in S-EL1 */ 59 #define ARM_SP_IMAGE_MMAP MAP_REGION2( \ 60 ARM_SP_IMAGE_BASE, \ 61 ARM_SP_IMAGE_BASE, \ 62 ARM_SP_IMAGE_SIZE, \ 63 MT_CODE | MT_SECURE | MT_USER, \ 64 PAGE_SIZE) 65 #endif 66 67 /* 68 * Memory shared between EL3 and S-EL0. It is used by EL3 to push data into 69 * S-EL0, so it is mapped with RW permission from EL3 and with RO permission 70 * from S-EL0. Placed after SPM Payload memory. 71 */ 72 #define PLAT_SPM_BUF_BASE (ARM_SP_IMAGE_BASE + ARM_SP_IMAGE_SIZE) 73 #define PLAT_SPM_BUF_SIZE ULL(0x100000) 74 75 #define ARM_SPM_BUF_EL3_MMAP MAP_REGION_FLAT( \ 76 PLAT_SPM_BUF_BASE, \ 77 PLAT_SPM_BUF_SIZE, \ 78 MT_RW_DATA | MT_SECURE) 79 #define ARM_SPM_BUF_EL0_MMAP MAP_REGION2( \ 80 PLAT_SPM_BUF_BASE, \ 81 PLAT_SPM_BUF_BASE, \ 82 PLAT_SPM_BUF_SIZE, \ 83 MT_RO_DATA | MT_SECURE | MT_USER,\ 84 PAGE_SIZE) 85 86 /* 87 * Memory shared between Normal world and S-EL0 for passing data during service 88 * requests. Mapped as RW and NS. Placed after the shared memory between EL3 and 89 * S-EL0. 90 */ 91 #define ARM_SP_IMAGE_NS_BUF_BASE (PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE) 92 #define ARM_SP_IMAGE_NS_BUF_SIZE ULL(0x10000) 93 #define ARM_SP_IMAGE_NS_BUF_MMAP MAP_REGION2( \ 94 ARM_SP_IMAGE_NS_BUF_BASE, \ 95 ARM_SP_IMAGE_NS_BUF_BASE, \ 96 ARM_SP_IMAGE_NS_BUF_SIZE, \ 97 MT_RW_DATA | MT_NS | MT_USER, \ 98 PAGE_SIZE) 99 100 /* 101 * RW memory, which uses the remaining Trusted DRAM. Placed after the memory 102 * shared between Secure and Non-secure worlds, or after the platform specific 103 * buffers, if defined. First there is the stack memory for all CPUs and then 104 * there is the common heap memory. Both are mapped with RW permissions. 105 */ 106 #define PLAT_SP_IMAGE_STACK_BASE PLAT_ARM_SP_IMAGE_STACK_BASE 107 #define PLAT_SP_IMAGE_STACK_PCPU_SIZE ULL(0x2000) 108 #define ARM_SP_IMAGE_STACK_TOTAL_SIZE (PLATFORM_CORE_COUNT * \ 109 PLAT_SP_IMAGE_STACK_PCPU_SIZE) 110 111 #define ARM_SP_IMAGE_HEAP_BASE (PLAT_SP_IMAGE_STACK_BASE + \ 112 ARM_SP_IMAGE_STACK_TOTAL_SIZE) 113 #define ARM_SP_IMAGE_HEAP_SIZE (ARM_SP_IMAGE_LIMIT - ARM_SP_IMAGE_HEAP_BASE) 114 115 #define ARM_SP_IMAGE_RW_MMAP MAP_REGION2( \ 116 PLAT_SP_IMAGE_STACK_BASE, \ 117 PLAT_SP_IMAGE_STACK_BASE, \ 118 (ARM_SP_IMAGE_LIMIT - \ 119 PLAT_SP_IMAGE_STACK_BASE), \ 120 MT_RW_DATA | MT_SECURE | MT_USER,\ 121 PAGE_SIZE) 122 123 /* Total number of memory regions with distinct properties */ 124 #define ARM_SP_IMAGE_NUM_MEM_REGIONS 6 125 126 #endif /* SPM_DEPRECATED */ 127 128 /* Cookies passed to the Secure Partition at boot. Not used by ARM platforms. */ 129 #define PLAT_SPM_COOKIE_0 ULL(0) 130 #define PLAT_SPM_COOKIE_1 ULL(0) 131 132 /* 133 * Max number of elements supported by SPM in this platform. The defines below 134 * are used to allocate memory at compile time for different arrays in SPM. 135 */ 136 #define PLAT_SPM_MAX_PARTITIONS U(2) 137 138 #define PLAT_SPM_MEM_REGIONS_MAX U(80) 139 #define PLAT_SPM_NOTIFICATIONS_MAX U(30) 140 #define PLAT_SPM_SERVICES_MAX U(30) 141 142 #define PLAT_SPCI_HANDLES_MAX_NUM U(20) 143 #define PLAT_SPM_RESPONSES_MAX U(30) 144 145 #endif /* ARM_SPM_DEF_H */ 146