1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <console.h> 11 #include <debug.h> 12 #include <desc_image_load.h> 13 #include <dw_mmc.h> 14 #include <errno.h> 15 #include <generic_delay_timer.h> 16 #include <mmc.h> 17 #include <mmio.h> 18 #include <optee_utils.h> 19 #include <partition/partition.h> 20 #include <platform.h> 21 #include <string.h> 22 #include "hi3798cv200.h" 23 #include "plat_private.h" 24 25 /* Memory ranges for code and read only data sections */ 26 #define BL2_RO_BASE (unsigned long)(&__RO_START__) 27 #define BL2_RO_LIMIT (unsigned long)(&__RO_END__) 28 29 /* Memory ranges for coherent memory section */ 30 #define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 31 #define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 32 33 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 34 35 /******************************************************************************* 36 * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol. 37 * Return 0 on success, -1 otherwise. 38 ******************************************************************************/ 39 int plat_poplar_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info) 40 { 41 /* 42 * This platform has no SCP_BL2 yet 43 */ 44 return 0; 45 } 46 47 /******************************************************************************* 48 * Gets SPSR for BL32 entry 49 ******************************************************************************/ 50 uint32_t poplar_get_spsr_for_bl32_entry(void) 51 { 52 /* 53 * The Secure Payload Dispatcher service is responsible for 54 * setting the SPSR prior to entry into the BL3-2 image. 55 */ 56 return 0; 57 } 58 59 /******************************************************************************* 60 * Gets SPSR for BL33 entry 61 ******************************************************************************/ 62 #ifndef AARCH32 63 uint32_t poplar_get_spsr_for_bl33_entry(void) 64 { 65 unsigned long el_status; 66 unsigned int mode; 67 uint32_t spsr; 68 69 /* Figure out what mode we enter the non-secure world in */ 70 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 71 el_status &= ID_AA64PFR0_ELX_MASK; 72 73 mode = (el_status) ? MODE_EL2 : MODE_EL1; 74 75 /* 76 * TODO: Consider the possibility of specifying the SPSR in 77 * the FIP ToC and allowing the platform to have a say as 78 * well. 79 */ 80 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 81 return spsr; 82 } 83 #else 84 uint32_t poplar_get_spsr_for_bl33_entry(void) 85 { 86 unsigned int hyp_status, mode, spsr; 87 88 hyp_status = GET_VIRT_EXT(read_id_pfr1()); 89 90 mode = (hyp_status) ? MODE32_hyp : MODE32_svc; 91 92 /* 93 * TODO: Consider the possibility of specifying the SPSR in 94 * the FIP ToC and allowing the platform to have a say as 95 * well. 96 */ 97 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, 98 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); 99 return spsr; 100 } 101 #endif /* AARCH32 */ 102 103 int poplar_bl2_handle_post_image_load(unsigned int image_id) 104 { 105 int err = 0; 106 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 107 #ifdef SPD_opteed 108 bl_mem_params_node_t *pager_mem_params = NULL; 109 bl_mem_params_node_t *paged_mem_params = NULL; 110 #endif 111 112 assert(bl_mem_params); 113 114 switch (image_id) { 115 #ifdef AARCH64 116 case BL32_IMAGE_ID: 117 #ifdef SPD_opteed 118 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 119 assert(pager_mem_params); 120 121 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 122 assert(paged_mem_params); 123 124 err = parse_optee_header(&bl_mem_params->ep_info, 125 &pager_mem_params->image_info, 126 &paged_mem_params->image_info); 127 if (err != 0) { 128 WARN("OPTEE header parse error.\n"); 129 } 130 131 /* 132 * OP-TEE expect to receive DTB address in x2. 133 * This will be copied into x2 by dispatcher. 134 * Set this (arg3) if necessary 135 */ 136 /* bl_mem_params->ep_info.args.arg3 = PLAT_HIKEY_DT_BASE; */ 137 #endif 138 bl_mem_params->ep_info.spsr = poplar_get_spsr_for_bl32_entry(); 139 break; 140 #endif 141 142 case BL33_IMAGE_ID: 143 /* BL33 expects to receive the primary CPU MPID (through r0) */ 144 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 145 bl_mem_params->ep_info.spsr = poplar_get_spsr_for_bl33_entry(); 146 break; 147 148 #ifdef SCP_BL2_BASE 149 case SCP_BL2_IMAGE_ID: 150 /* The subsequent handling of SCP_BL2 is platform specific */ 151 err = plat_poplar_bl2_handle_scp_bl2(&bl_mem_params->image_info); 152 if (err) { 153 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 154 } 155 break; 156 #endif 157 default: 158 /* Do nothing in default case */ 159 break; 160 } 161 162 return err; 163 } 164 165 /******************************************************************************* 166 * This function can be used by the platforms to update/use image 167 * information for given `image_id`. 168 ******************************************************************************/ 169 int bl2_plat_handle_post_image_load(unsigned int image_id) 170 { 171 return poplar_bl2_handle_post_image_load(image_id); 172 } 173 174 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, 175 u_register_t arg2, u_register_t arg3) 176 { 177 struct meminfo *mem_layout = (struct meminfo *)arg1; 178 #if !POPLAR_RECOVERY 179 struct mmc_device_info info; 180 181 dw_mmc_params_t params = EMMC_INIT_PARAMS(POPLAR_EMMC_DESC_BASE); 182 #endif 183 184 console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE); 185 186 /* Enable arch timer */ 187 generic_delay_timer_init(); 188 189 bl2_tzram_layout = *mem_layout; 190 191 #if !POPLAR_RECOVERY 192 /* SoC-specific emmc register are initialized/configured by bootrom */ 193 INFO("BL2: initializing emmc\n"); 194 info.mmc_dev_type = MMC_IS_EMMC; 195 dw_mmc_init(¶ms, &info); 196 #endif 197 198 plat_io_setup(); 199 } 200 201 void bl2_plat_arch_setup(void) 202 { 203 plat_configure_mmu_el1(bl2_tzram_layout.total_base, 204 bl2_tzram_layout.total_size, 205 BL2_RO_BASE, 206 BL2_RO_LIMIT, 207 BL2_COHERENT_RAM_BASE, 208 BL2_COHERENT_RAM_LIMIT); 209 } 210 211 void bl2_platform_setup(void) 212 { 213 } 214 215 uintptr_t plat_get_ns_image_entrypoint(void) 216 { 217 #ifdef PRELOADED_BL33_BASE 218 return PRELOADED_BL33_BASE; 219 #else 220 return PLAT_POPLAR_NS_IMAGE_OFFSET; 221 #endif 222 } 223