1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <console.h> 11 #include <debug.h> 12 #include <delay_timer.h> 13 #include <desc_image_load.h> 14 #include <dw_mmc.h> 15 #include <errno.h> 16 #include <hi6220.h> 17 #include <hisi_mcu.h> 18 #include <hisi_sram_map.h> 19 #include <mmc.h> 20 #include <mmio.h> 21 #ifdef SPD_opteed 22 #include <optee_utils.h> 23 #endif 24 #include <platform.h> 25 #include <platform_def.h> /* also includes hikey_def.h and hikey_layout.h*/ 26 #include <string.h> 27 28 #include "hikey_private.h" 29 30 /* 31 * The next 2 constants identify the extents of the code & RO data region. 32 * These addresses are used by the MMU setup code and therefore they must be 33 * page-aligned. It is the responsibility of the linker script to ensure that 34 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. 35 */ 36 #define BL2_RO_BASE (unsigned long)(&__RO_START__) 37 #define BL2_RO_LIMIT (unsigned long)(&__RO_END__) 38 39 #define BL2_RW_BASE (BL2_RO_LIMIT) 40 41 /* 42 * The next 2 constants identify the extents of the coherent memory region. 43 * These addresses are used by the MMU setup code and therefore they must be 44 * page-aligned. It is the responsibility of the linker script to ensure that 45 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 46 * page-aligned addresses. 47 */ 48 #define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 49 #define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 50 51 static meminfo_t bl2_el3_tzram_layout; 52 53 enum { 54 BOOT_MODE_RECOVERY = 0, 55 BOOT_MODE_NORMAL, 56 BOOT_MODE_MASK = 1, 57 }; 58 59 /******************************************************************************* 60 * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol. 61 * Return 0 on success, -1 otherwise. 62 ******************************************************************************/ 63 int plat_hikey_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info) 64 { 65 /* Enable MCU SRAM */ 66 hisi_mcu_enable_sram(); 67 68 /* Load MCU binary into SRAM */ 69 hisi_mcu_load_image(scp_bl2_image_info->image_base, 70 scp_bl2_image_info->image_size); 71 /* Let MCU running */ 72 hisi_mcu_start_run(); 73 74 INFO("%s: MCU PC is at 0x%x\n", 75 __func__, mmio_read_32(AO_SC_MCU_SUBSYS_STAT2)); 76 INFO("%s: AO_SC_PERIPH_CLKSTAT4 is 0x%x\n", 77 __func__, mmio_read_32(AO_SC_PERIPH_CLKSTAT4)); 78 return 0; 79 } 80 81 /******************************************************************************* 82 * Gets SPSR for BL32 entry 83 ******************************************************************************/ 84 uint32_t hikey_get_spsr_for_bl32_entry(void) 85 { 86 /* 87 * The Secure Payload Dispatcher service is responsible for 88 * setting the SPSR prior to entry into the BL3-2 image. 89 */ 90 return 0; 91 } 92 93 /******************************************************************************* 94 * Gets SPSR for BL33 entry 95 ******************************************************************************/ 96 #ifndef AARCH32 97 uint32_t hikey_get_spsr_for_bl33_entry(void) 98 { 99 unsigned int mode; 100 uint32_t spsr; 101 102 /* Figure out what mode we enter the non-secure world in */ 103 mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1; 104 105 /* 106 * TODO: Consider the possibility of specifying the SPSR in 107 * the FIP ToC and allowing the platform to have a say as 108 * well. 109 */ 110 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 111 return spsr; 112 } 113 #else 114 uint32_t hikey_get_spsr_for_bl33_entry(void) 115 { 116 unsigned int hyp_status, mode, spsr; 117 118 hyp_status = GET_VIRT_EXT(read_id_pfr1()); 119 120 mode = (hyp_status) ? MODE32_hyp : MODE32_svc; 121 122 /* 123 * TODO: Consider the possibility of specifying the SPSR in 124 * the FIP ToC and allowing the platform to have a say as 125 * well. 126 */ 127 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, 128 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); 129 return spsr; 130 } 131 #endif /* AARCH32 */ 132 133 int hikey_bl2_handle_post_image_load(unsigned int image_id) 134 { 135 int err = 0; 136 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 137 #ifdef SPD_opteed 138 bl_mem_params_node_t *pager_mem_params = NULL; 139 bl_mem_params_node_t *paged_mem_params = NULL; 140 #endif 141 assert(bl_mem_params); 142 143 switch (image_id) { 144 #ifdef AARCH64 145 case BL32_IMAGE_ID: 146 #ifdef SPD_opteed 147 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 148 assert(pager_mem_params); 149 150 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 151 assert(paged_mem_params); 152 153 err = parse_optee_header(&bl_mem_params->ep_info, 154 &pager_mem_params->image_info, 155 &paged_mem_params->image_info); 156 if (err != 0) { 157 WARN("OPTEE header parse error.\n"); 158 } 159 #endif 160 bl_mem_params->ep_info.spsr = hikey_get_spsr_for_bl32_entry(); 161 break; 162 #endif 163 164 case BL33_IMAGE_ID: 165 /* BL33 expects to receive the primary CPU MPID (through r0) */ 166 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 167 bl_mem_params->ep_info.spsr = hikey_get_spsr_for_bl33_entry(); 168 break; 169 170 #ifdef SCP_BL2_BASE 171 case SCP_BL2_IMAGE_ID: 172 /* The subsequent handling of SCP_BL2 is platform specific */ 173 err = plat_hikey_bl2_handle_scp_bl2(&bl_mem_params->image_info); 174 if (err) { 175 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 176 } 177 break; 178 #endif 179 default: 180 /* Do nothing in default case */ 181 break; 182 } 183 184 return err; 185 } 186 187 /******************************************************************************* 188 * This function can be used by the platforms to update/use image 189 * information for given `image_id`. 190 ******************************************************************************/ 191 int bl2_plat_handle_post_image_load(unsigned int image_id) 192 { 193 return hikey_bl2_handle_post_image_load(image_id); 194 } 195 196 static void reset_dwmmc_clk(void) 197 { 198 unsigned int data; 199 200 /* disable mmc0 bus clock */ 201 mmio_write_32(PERI_SC_PERIPH_CLKDIS0, PERI_CLK0_MMC0); 202 do { 203 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); 204 } while (data & PERI_CLK0_MMC0); 205 /* enable mmc0 bus clock */ 206 mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK0_MMC0); 207 do { 208 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); 209 } while (!(data & PERI_CLK0_MMC0)); 210 /* reset mmc0 clock domain */ 211 mmio_write_32(PERI_SC_PERIPH_RSTEN0, PERI_RST0_MMC0); 212 213 /* bypass mmc0 clock phase */ 214 data = mmio_read_32(PERI_SC_PERIPH_CTRL2); 215 data |= 3; 216 mmio_write_32(PERI_SC_PERIPH_CTRL2, data); 217 218 /* disable low power */ 219 data = mmio_read_32(PERI_SC_PERIPH_CTRL13); 220 data |= 1 << 3; 221 mmio_write_32(PERI_SC_PERIPH_CTRL13, data); 222 do { 223 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0); 224 } while (!(data & PERI_RST0_MMC0)); 225 226 /* unreset mmc0 clock domain */ 227 mmio_write_32(PERI_SC_PERIPH_RSTDIS0, PERI_RST0_MMC0); 228 do { 229 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0); 230 } while (data & PERI_RST0_MMC0); 231 } 232 233 static void hikey_boardid_init(void) 234 { 235 u_register_t midr; 236 237 midr = read_midr(); 238 mmio_write_32(MEMORY_AXI_CHIP_ADDR, midr); 239 INFO("[BDID] [%x] midr: 0x%x\n", MEMORY_AXI_CHIP_ADDR, 240 (unsigned int)midr); 241 242 mmio_write_32(MEMORY_AXI_BOARD_TYPE_ADDR, 0); 243 mmio_write_32(MEMORY_AXI_BOARD_ID_ADDR, 0x2b); 244 245 mmio_write_32(ACPU_ARM64_FLAGA, 0x1234); 246 mmio_write_32(ACPU_ARM64_FLAGB, 0x5678); 247 } 248 249 static void hikey_sd_init(void) 250 { 251 /* switch pinmux to SD */ 252 mmio_write_32(IOMG_SD_CLK, IOMG_MUX_FUNC0); 253 mmio_write_32(IOMG_SD_CMD, IOMG_MUX_FUNC0); 254 mmio_write_32(IOMG_SD_DATA0, IOMG_MUX_FUNC0); 255 mmio_write_32(IOMG_SD_DATA1, IOMG_MUX_FUNC0); 256 mmio_write_32(IOMG_SD_DATA2, IOMG_MUX_FUNC0); 257 mmio_write_32(IOMG_SD_DATA3, IOMG_MUX_FUNC0); 258 259 mmio_write_32(IOCG_SD_CLK, IOCG_INPUT_16MA); 260 mmio_write_32(IOCG_SD_CMD, IOCG_INPUT_12MA); 261 mmio_write_32(IOCG_SD_DATA0, IOCG_INPUT_12MA); 262 mmio_write_32(IOCG_SD_DATA1, IOCG_INPUT_12MA); 263 mmio_write_32(IOCG_SD_DATA2, IOCG_INPUT_12MA); 264 mmio_write_32(IOCG_SD_DATA3, IOCG_INPUT_12MA); 265 266 /* set SD Card detect as nopull */ 267 mmio_write_32(IOCG_GPIO8, 0); 268 } 269 270 static void hikey_jumper_init(void) 271 { 272 /* set jumper detect as nopull */ 273 mmio_write_32(IOCG_GPIO24, 0); 274 /* set jumper detect as GPIO */ 275 mmio_write_32(IOMG_GPIO24, IOMG_MUX_FUNC0); 276 } 277 278 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, 279 u_register_t arg3, u_register_t arg4) 280 { 281 /* Initialize the console to provide early debug support */ 282 console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE); 283 /* 284 * Allow BL2 to see the whole Trusted RAM. 285 */ 286 bl2_el3_tzram_layout.total_base = BL2_RW_BASE; 287 bl2_el3_tzram_layout.total_size = BL31_LIMIT - BL2_RW_BASE; 288 } 289 290 void bl2_el3_plat_arch_setup(void) 291 { 292 hikey_init_mmu_el3(bl2_el3_tzram_layout.total_base, 293 bl2_el3_tzram_layout.total_size, 294 BL2_RO_BASE, 295 BL2_RO_LIMIT, 296 BL2_COHERENT_RAM_BASE, 297 BL2_COHERENT_RAM_LIMIT); 298 } 299 300 void bl2_platform_setup(void) 301 { 302 dw_mmc_params_t params; 303 struct mmc_device_info info; 304 305 hikey_sp804_init(); 306 hikey_gpio_init(); 307 hikey_pmussi_init(); 308 hikey_hi6553_init(); 309 /* Clear SRAM since it'll be used by MCU right now. */ 310 memset((void *)SRAM_BASE, 0, SRAM_SIZE); 311 312 dsb(); 313 hikey_ddr_init(DDR_FREQ_800M); 314 hikey_security_setup(); 315 316 hikey_boardid_init(); 317 init_acpu_dvfs(); 318 hikey_rtc_init(); 319 hikey_sd_init(); 320 hikey_jumper_init(); 321 322 hikey_mmc_pll_init(); 323 324 /* Clean SRAM before MCU used */ 325 clean_dcache_range(SRAM_BASE, SRAM_SIZE); 326 327 reset_dwmmc_clk(); 328 memset(¶ms, 0, sizeof(dw_mmc_params_t)); 329 params.reg_base = DWMMC0_BASE; 330 params.desc_base = HIKEY_MMC_DESC_BASE; 331 params.desc_size = 1 << 20; 332 params.clk_rate = 24 * 1000 * 1000; 333 params.bus_width = MMC_BUS_WIDTH_8; 334 params.flags = MMC_FLAG_CMD23; 335 info.mmc_dev_type = MMC_IS_EMMC; 336 dw_mmc_init(¶ms, &info); 337 mdelay(5); 338 339 hikey_io_setup(); 340 } 341