1 /* 2 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #include <errno.h> 8 9 #include <libfdt.h> 10 11 #include <platform_def.h> 12 13 #include <arch_helpers.h> 14 #include <common/debug.h> 15 #include <drivers/st/stm32mp1_clk.h> 16 #include <drivers/st/stm32mp1_ddr.h> 17 #include <drivers/st/stm32mp1_ddr_helpers.h> 18 #include <drivers/st/stm32mp1_ram.h> 19 #include <drivers/st/stm32mp1_rcc.h> 20 #include <dt-bindings/clock/stm32mp1-clks.h> 21 #include <lib/mmio.h> 22 23 #include <boot_api.h> 24 #include <stm32mp1_dt.h> 25 #include <stm32mp1_private.h> 26 27 #define DDR_PATTERN 0xAAAAAAAAU 28 #define DDR_ANTIPATTERN 0x55555555U 29 30 static struct ddr_info ddr_priv_data; 31 32 int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint16_t mem_speed) 33 { 34 unsigned long ddrphy_clk, ddr_clk, mem_speed_hz; 35 36 ddr_enable_clock(); 37 38 ddrphy_clk = stm32mp1_clk_get_rate(DDRPHYC); 39 40 VERBOSE("DDR: mem_speed (%d MHz), RCC %ld MHz\n", 41 mem_speed, ddrphy_clk / 1000U / 1000U); 42 43 mem_speed_hz = (uint32_t)mem_speed * 1000U * 1000U; 44 45 /* Max 10% frequency delta */ 46 if (ddrphy_clk > mem_speed_hz) { 47 ddr_clk = ddrphy_clk - mem_speed_hz; 48 } else { 49 ddr_clk = mem_speed_hz - ddrphy_clk; 50 } 51 if (ddr_clk > mem_speed_hz) { 52 ERROR("DDR expected freq %d MHz, current is %ld MHz\n", 53 mem_speed, ddrphy_clk / 1000U / 1000U); 54 return -1; 55 } 56 return 0; 57 } 58 59 /******************************************************************************* 60 * This function tests the DDR data bus wiring. 61 * This is inspired from the Data Bus Test algorithm written by Michael Barr 62 * in "Programming Embedded Systems in C and C++" book. 63 * resources.oreilly.com/examples/9781565923546/blob/master/Chapter6/ 64 * File: memtest.c - This source code belongs to Public Domain. 65 * Returns 0 if success, and address value else. 66 ******************************************************************************/ 67 static uint32_t ddr_test_data_bus(void) 68 { 69 uint32_t pattern; 70 71 for (pattern = 1U; pattern != 0U; pattern <<= 1) { 72 mmio_write_32(STM32MP1_DDR_BASE, pattern); 73 74 if (mmio_read_32(STM32MP1_DDR_BASE) != pattern) { 75 return (uint32_t)STM32MP1_DDR_BASE; 76 } 77 } 78 79 return 0; 80 } 81 82 /******************************************************************************* 83 * This function tests the DDR address bus wiring. 84 * This is inspired from the Data Bus Test algorithm written by Michael Barr 85 * in "Programming Embedded Systems in C and C++" book. 86 * resources.oreilly.com/examples/9781565923546/blob/master/Chapter6/ 87 * File: memtest.c - This source code belongs to Public Domain. 88 * Returns 0 if success, and address value else. 89 ******************************************************************************/ 90 static uint32_t ddr_test_addr_bus(void) 91 { 92 uint64_t addressmask = (ddr_priv_data.info.size - 1U); 93 uint64_t offset; 94 uint64_t testoffset = 0; 95 96 /* Write the default pattern at each of the power-of-two offsets. */ 97 for (offset = sizeof(uint32_t); (offset & addressmask) != 0U; 98 offset <<= 1) { 99 mmio_write_32(STM32MP1_DDR_BASE + (uint32_t)offset, 100 DDR_PATTERN); 101 } 102 103 /* Check for address bits stuck high. */ 104 mmio_write_32(STM32MP1_DDR_BASE + (uint32_t)testoffset, 105 DDR_ANTIPATTERN); 106 107 for (offset = sizeof(uint32_t); (offset & addressmask) != 0U; 108 offset <<= 1) { 109 if (mmio_read_32(STM32MP1_DDR_BASE + (uint32_t)offset) != 110 DDR_PATTERN) { 111 return (uint32_t)(STM32MP1_DDR_BASE + offset); 112 } 113 } 114 115 mmio_write_32(STM32MP1_DDR_BASE + (uint32_t)testoffset, DDR_PATTERN); 116 117 /* Check for address bits stuck low or shorted. */ 118 for (testoffset = sizeof(uint32_t); (testoffset & addressmask) != 0U; 119 testoffset <<= 1) { 120 mmio_write_32(STM32MP1_DDR_BASE + (uint32_t)testoffset, 121 DDR_ANTIPATTERN); 122 123 if (mmio_read_32(STM32MP1_DDR_BASE) != DDR_PATTERN) { 124 return STM32MP1_DDR_BASE; 125 } 126 127 for (offset = sizeof(uint32_t); (offset & addressmask) != 0U; 128 offset <<= 1) { 129 if ((mmio_read_32(STM32MP1_DDR_BASE + 130 (uint32_t)offset) != DDR_PATTERN) && 131 (offset != testoffset)) { 132 return (uint32_t)(STM32MP1_DDR_BASE + offset); 133 } 134 } 135 136 mmio_write_32(STM32MP1_DDR_BASE + (uint32_t)testoffset, 137 DDR_PATTERN); 138 } 139 140 return 0; 141 } 142 143 /******************************************************************************* 144 * This function checks the DDR size. It has to be run with Data Cache off. 145 * This test is run before data have been put in DDR, and is only done for 146 * cold boot. The DDR data can then be overwritten, and it is not useful to 147 * restore its content. 148 * Returns DDR computed size. 149 ******************************************************************************/ 150 static uint32_t ddr_check_size(void) 151 { 152 uint32_t offset = sizeof(uint32_t); 153 154 mmio_write_32(STM32MP1_DDR_BASE, DDR_PATTERN); 155 156 while (offset < STM32MP1_DDR_MAX_SIZE) { 157 mmio_write_32(STM32MP1_DDR_BASE + offset, DDR_ANTIPATTERN); 158 dsb(); 159 160 if (mmio_read_32(STM32MP1_DDR_BASE) != DDR_PATTERN) { 161 break; 162 } 163 164 offset <<= 1; 165 } 166 167 INFO("Memory size = 0x%x (%d MB)\n", offset, offset / (1024U * 1024U)); 168 169 return offset; 170 } 171 172 static int stm32mp1_ddr_setup(void) 173 { 174 struct ddr_info *priv = &ddr_priv_data; 175 int ret; 176 struct stm32mp1_ddr_config config; 177 int node, len; 178 uint32_t tamp_clk_off = 0, uret, idx; 179 void *fdt; 180 181 #define PARAM(x, y) \ 182 { \ 183 .name = x, \ 184 .offset = offsetof(struct stm32mp1_ddr_config, y), \ 185 .size = sizeof(config.y) / sizeof(uint32_t) \ 186 } 187 188 #define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x) 189 #define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x) 190 191 const struct { 192 const char *name; /* Name in DT */ 193 const uint32_t offset; /* Offset in config struct */ 194 const uint32_t size; /* Size of parameters */ 195 } param[] = { 196 CTL_PARAM(reg), 197 CTL_PARAM(timing), 198 CTL_PARAM(map), 199 CTL_PARAM(perf), 200 PHY_PARAM(reg), 201 PHY_PARAM(timing), 202 PHY_PARAM(cal) 203 }; 204 205 if (fdt_get_address(&fdt) == 0) { 206 return -ENOENT; 207 } 208 209 node = fdt_node_offset_by_compatible(fdt, -1, DT_DDR_COMPAT); 210 if (node < 0) { 211 ERROR("%s: Cannot read DDR node in DT\n", __func__); 212 return -EINVAL; 213 } 214 215 config.info.speed = 216 (uint16_t)fdt_read_uint32_default(node, "st,mem-speed", 217 STM32MP1_DDR_SPEED_DFLT); 218 config.info.size = fdt_read_uint32_default(node, "st,mem-size", 219 STM32MP1_DDR_SIZE_DFLT); 220 config.info.name = fdt_getprop(fdt, node, "st,mem-name", &len); 221 if (config.info.name == NULL) { 222 VERBOSE("%s: no st,mem-name\n", __func__); 223 return -EINVAL; 224 } 225 INFO("RAM: %s\n", config.info.name); 226 227 for (idx = 0; idx < ARRAY_SIZE(param); idx++) { 228 ret = fdt_read_uint32_array(node, param[idx].name, 229 (void *)((uint32_t)&config + 230 param[idx].offset), 231 param[idx].size); 232 233 VERBOSE("%s: %s[0x%x] = %d\n", __func__, 234 param[idx].name, param[idx].size, ret); 235 if (ret != 0) { 236 ERROR("%s: Cannot read %s\n", 237 __func__, param[idx].name); 238 return -EINVAL; 239 } 240 } 241 242 if (!stm32mp1_clk_is_enabled(RTCAPB)) { 243 tamp_clk_off = 1; 244 if (stm32mp1_clk_enable(RTCAPB) != 0) { 245 return -EINVAL; 246 } 247 } 248 249 if (tamp_clk_off != 0U) { 250 if (stm32mp1_clk_disable(RTCAPB) != 0) { 251 return -EINVAL; 252 } 253 } 254 255 /* Disable axidcg clock gating during init */ 256 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_AXIDCGEN); 257 258 stm32mp1_ddr_init(priv, &config); 259 260 /* Enable axidcg clock gating */ 261 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_AXIDCGEN); 262 263 priv->info.size = config.info.size; 264 265 VERBOSE("%s : ram size(%x, %x)\n", __func__, 266 (uint32_t)priv->info.base, (uint32_t)priv->info.size); 267 268 dcsw_op_all(DC_OP_CISW); 269 write_sctlr(read_sctlr() & ~SCTLR_C_BIT); 270 271 uret = ddr_test_data_bus(); 272 if (uret != 0U) { 273 ERROR("DDR data bus test: can't access memory @ 0x%x\n", 274 uret); 275 panic(); 276 } 277 278 uret = ddr_test_addr_bus(); 279 if (uret != 0U) { 280 ERROR("DDR addr bus test: can't access memory @ 0x%x\n", 281 uret); 282 panic(); 283 } 284 285 uret = ddr_check_size(); 286 if (uret < config.info.size) { 287 ERROR("DDR size: 0x%x does not match DT config: 0x%x\n", 288 uret, config.info.size); 289 panic(); 290 } 291 292 write_sctlr(read_sctlr() | SCTLR_C_BIT); 293 294 return 0; 295 } 296 297 int stm32mp1_ddr_probe(void) 298 { 299 struct ddr_info *priv = &ddr_priv_data; 300 301 VERBOSE("STM32MP DDR probe\n"); 302 303 priv->ctl = (struct stm32mp1_ddrctl *)DDRCTRL_BASE; 304 priv->phy = (struct stm32mp1_ddrphy *)DDRPHYC_BASE; 305 priv->pwr = PWR_BASE; 306 priv->rcc = RCC_BASE; 307 308 priv->info.base = STM32MP1_DDR_BASE; 309 priv->info.size = 0; 310 311 return stm32mp1_ddr_setup(); 312 } 313