1/* 2 * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <assert_macros.S> 9#include <bl_common.h> 10#include <cortex_a57.h> 11#include <cpu_macros.S> 12#include <debug.h> 13#include <plat_macros.S> 14 15 /* --------------------------------------------- 16 * Disable L1 data cache and unified L2 cache 17 * --------------------------------------------- 18 */ 19func cortex_a57_disable_dcache 20 mrs x1, sctlr_el3 21 bic x1, x1, #SCTLR_C_BIT 22 msr sctlr_el3, x1 23 isb 24 ret 25endfunc cortex_a57_disable_dcache 26 27 /* --------------------------------------------- 28 * Disable all types of L2 prefetches. 29 * --------------------------------------------- 30 */ 31func cortex_a57_disable_l2_prefetch 32 mrs x0, CPUECTLR_EL1 33 orr x0, x0, #CPUECTLR_DIS_TWD_ACC_PFTCH_BIT 34 mov x1, #CPUECTLR_L2_IPFTCH_DIST_MASK 35 orr x1, x1, #CPUECTLR_L2_DPFTCH_DIST_MASK 36 bic x0, x0, x1 37 msr CPUECTLR_EL1, x0 38 isb 39 dsb ish 40 ret 41endfunc cortex_a57_disable_l2_prefetch 42 43 /* --------------------------------------------- 44 * Disable intra-cluster coherency 45 * --------------------------------------------- 46 */ 47func cortex_a57_disable_smp 48 mrs x0, CPUECTLR_EL1 49 bic x0, x0, #CPUECTLR_SMP_BIT 50 msr CPUECTLR_EL1, x0 51 ret 52endfunc cortex_a57_disable_smp 53 54 /* --------------------------------------------- 55 * Disable debug interfaces 56 * --------------------------------------------- 57 */ 58func cortex_a57_disable_ext_debug 59 mov x0, #1 60 msr osdlr_el1, x0 61 isb 62 dsb sy 63 ret 64endfunc cortex_a57_disable_ext_debug 65 66 /* -------------------------------------------------- 67 * Errata Workaround for Cortex A57 Errata #806969. 68 * This applies only to revision r0p0 of Cortex A57. 69 * Inputs: 70 * x0: variant[4:7] and revision[0:3] of current cpu. 71 * Shall clobber: x0-x17 72 * -------------------------------------------------- 73 */ 74func errata_a57_806969_wa 75 /* 76 * Compare x0 against revision r0p0 77 */ 78 mov x17, x30 79 bl check_errata_806969 80 cbz x0, 1f 81 mrs x1, CPUACTLR_EL1 82 orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA 83 msr CPUACTLR_EL1, x1 841: 85 ret x17 86endfunc errata_a57_806969_wa 87 88func check_errata_806969 89 mov x1, #0x00 90 b cpu_rev_var_ls 91endfunc check_errata_806969 92 93 /* --------------------------------------------------- 94 * Errata Workaround for Cortex A57 Errata #813419. 95 * This applies only to revision r0p0 of Cortex A57. 96 * --------------------------------------------------- 97 */ 98func check_errata_813419 99 /* 100 * Even though this is only needed for revision r0p0, it 101 * is always applied due to limitations of the current 102 * errata framework. 103 */ 104 mov x0, #ERRATA_APPLIES 105 ret 106endfunc check_errata_813419 107 108 /* --------------------------------------------------- 109 * Errata Workaround for Cortex A57 Errata #813420. 110 * This applies only to revision r0p0 of Cortex A57. 111 * Inputs: 112 * x0: variant[4:7] and revision[0:3] of current cpu. 113 * Shall clobber: x0-x17 114 * --------------------------------------------------- 115 */ 116func errata_a57_813420_wa 117 /* 118 * Compare x0 against revision r0p0 119 */ 120 mov x17, x30 121 bl check_errata_813420 122 cbz x0, 1f 123 mrs x1, CPUACTLR_EL1 124 orr x1, x1, #CPUACTLR_DCC_AS_DCCI 125 msr CPUACTLR_EL1, x1 1261: 127 ret x17 128endfunc errata_a57_813420_wa 129 130func check_errata_813420 131 mov x1, #0x00 132 b cpu_rev_var_ls 133endfunc check_errata_813420 134 135 /* -------------------------------------------------------------------- 136 * Disable the over-read from the LDNP instruction. 137 * 138 * This applies to all revisions <= r1p2. The performance degradation 139 * observed with LDNP/STNP has been fixed on r1p3 and onwards. 140 * 141 * Inputs: 142 * x0: variant[4:7] and revision[0:3] of current cpu. 143 * Shall clobber: x0-x17 144 * --------------------------------------------------------------------- 145 */ 146func a57_disable_ldnp_overread 147 /* 148 * Compare x0 against revision r1p2 149 */ 150 mov x17, x30 151 bl check_errata_disable_ldnp_overread 152 cbz x0, 1f 153 mrs x1, CPUACTLR_EL1 154 orr x1, x1, #CPUACTLR_DIS_OVERREAD 155 msr CPUACTLR_EL1, x1 1561: 157 ret x17 158endfunc a57_disable_ldnp_overread 159 160func check_errata_disable_ldnp_overread 161 mov x1, #0x12 162 b cpu_rev_var_ls 163endfunc check_errata_disable_ldnp_overread 164 165 /* --------------------------------------------------- 166 * Errata Workaround for Cortex A57 Errata #826974. 167 * This applies only to revision <= r1p1 of Cortex A57. 168 * Inputs: 169 * x0: variant[4:7] and revision[0:3] of current cpu. 170 * Shall clobber: x0-x17 171 * --------------------------------------------------- 172 */ 173func errata_a57_826974_wa 174 /* 175 * Compare x0 against revision r1p1 176 */ 177 mov x17, x30 178 bl check_errata_826974 179 cbz x0, 1f 180 mrs x1, CPUACTLR_EL1 181 orr x1, x1, #CPUACTLR_DIS_LOAD_PASS_DMB 182 msr CPUACTLR_EL1, x1 1831: 184 ret x17 185endfunc errata_a57_826974_wa 186 187func check_errata_826974 188 mov x1, #0x11 189 b cpu_rev_var_ls 190endfunc check_errata_826974 191 192 /* --------------------------------------------------- 193 * Errata Workaround for Cortex A57 Errata #826977. 194 * This applies only to revision <= r1p1 of Cortex A57. 195 * Inputs: 196 * x0: variant[4:7] and revision[0:3] of current cpu. 197 * Shall clobber: x0-x17 198 * --------------------------------------------------- 199 */ 200func errata_a57_826977_wa 201 /* 202 * Compare x0 against revision r1p1 203 */ 204 mov x17, x30 205 bl check_errata_826977 206 cbz x0, 1f 207 mrs x1, CPUACTLR_EL1 208 orr x1, x1, #CPUACTLR_GRE_NGRE_AS_NGNRE 209 msr CPUACTLR_EL1, x1 2101: 211 ret x17 212endfunc errata_a57_826977_wa 213 214func check_errata_826977 215 mov x1, #0x11 216 b cpu_rev_var_ls 217endfunc check_errata_826977 218 219 /* --------------------------------------------------- 220 * Errata Workaround for Cortex A57 Errata #828024. 221 * This applies only to revision <= r1p1 of Cortex A57. 222 * Inputs: 223 * x0: variant[4:7] and revision[0:3] of current cpu. 224 * Shall clobber: x0-x17 225 * --------------------------------------------------- 226 */ 227func errata_a57_828024_wa 228 /* 229 * Compare x0 against revision r1p1 230 */ 231 mov x17, x30 232 bl check_errata_828024 233 cbz x0, 1f 234 mrs x1, CPUACTLR_EL1 235 /* 236 * Setting the relevant bits in CPUACTLR_EL1 has to be done in 2 237 * instructions here because the resulting bitmask doesn't fit in a 238 * 16-bit value so it cannot be encoded in a single instruction. 239 */ 240 orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA 241 orr x1, x1, #(CPUACTLR_DIS_L1_STREAMING | CPUACTLR_DIS_STREAMING) 242 msr CPUACTLR_EL1, x1 2431: 244 ret x17 245endfunc errata_a57_828024_wa 246 247func check_errata_828024 248 mov x1, #0x11 249 b cpu_rev_var_ls 250endfunc check_errata_828024 251 252 /* --------------------------------------------------- 253 * Errata Workaround for Cortex A57 Errata #829520. 254 * This applies only to revision <= r1p2 of Cortex A57. 255 * Inputs: 256 * x0: variant[4:7] and revision[0:3] of current cpu. 257 * Shall clobber: x0-x17 258 * --------------------------------------------------- 259 */ 260func errata_a57_829520_wa 261 /* 262 * Compare x0 against revision r1p2 263 */ 264 mov x17, x30 265 bl check_errata_829520 266 cbz x0, 1f 267 mrs x1, CPUACTLR_EL1 268 orr x1, x1, #CPUACTLR_DIS_INDIRECT_PREDICTOR 269 msr CPUACTLR_EL1, x1 2701: 271 ret x17 272endfunc errata_a57_829520_wa 273 274func check_errata_829520 275 mov x1, #0x12 276 b cpu_rev_var_ls 277endfunc check_errata_829520 278 279 /* --------------------------------------------------- 280 * Errata Workaround for Cortex A57 Errata #833471. 281 * This applies only to revision <= r1p2 of Cortex A57. 282 * Inputs: 283 * x0: variant[4:7] and revision[0:3] of current cpu. 284 * Shall clobber: x0-x17 285 * --------------------------------------------------- 286 */ 287func errata_a57_833471_wa 288 /* 289 * Compare x0 against revision r1p2 290 */ 291 mov x17, x30 292 bl check_errata_833471 293 cbz x0, 1f 294 mrs x1, CPUACTLR_EL1 295 orr x1, x1, #CPUACTLR_FORCE_FPSCR_FLUSH 296 msr CPUACTLR_EL1, x1 2971: 298 ret x17 299endfunc errata_a57_833471_wa 300 301func check_errata_833471 302 mov x1, #0x12 303 b cpu_rev_var_ls 304endfunc check_errata_833471 305 306 /* ------------------------------------------------- 307 * The CPU Ops reset function for Cortex-A57. 308 * Shall clobber: x0-x19 309 * ------------------------------------------------- 310 */ 311func cortex_a57_reset_func 312 mov x19, x30 313 bl cpu_get_rev_var 314 mov x18, x0 315 316#if ERRATA_A57_806969 317 mov x0, x18 318 bl errata_a57_806969_wa 319#endif 320 321#if ERRATA_A57_813420 322 mov x0, x18 323 bl errata_a57_813420_wa 324#endif 325 326#if A57_DISABLE_NON_TEMPORAL_HINT 327 mov x0, x18 328 bl a57_disable_ldnp_overread 329#endif 330 331#if ERRATA_A57_826974 332 mov x0, x18 333 bl errata_a57_826974_wa 334#endif 335 336#if ERRATA_A57_826977 337 mov x0, x18 338 bl errata_a57_826977_wa 339#endif 340 341#if ERRATA_A57_828024 342 mov x0, x18 343 bl errata_a57_828024_wa 344#endif 345 346#if ERRATA_A57_829520 347 mov x0, x18 348 bl errata_a57_829520_wa 349#endif 350 351#if ERRATA_A57_833471 352 mov x0, x18 353 bl errata_a57_833471_wa 354#endif 355 356 /* --------------------------------------------- 357 * Enable the SMP bit. 358 * --------------------------------------------- 359 */ 360 mrs x0, CPUECTLR_EL1 361 orr x0, x0, #CPUECTLR_SMP_BIT 362 msr CPUECTLR_EL1, x0 363 isb 364 ret x19 365endfunc cortex_a57_reset_func 366 367 /* ---------------------------------------------------- 368 * The CPU Ops core power down function for Cortex-A57. 369 * ---------------------------------------------------- 370 */ 371func cortex_a57_core_pwr_dwn 372 mov x18, x30 373 374 /* --------------------------------------------- 375 * Turn off caches. 376 * --------------------------------------------- 377 */ 378 bl cortex_a57_disable_dcache 379 380 /* --------------------------------------------- 381 * Disable the L2 prefetches. 382 * --------------------------------------------- 383 */ 384 bl cortex_a57_disable_l2_prefetch 385 386 /* --------------------------------------------- 387 * Flush L1 caches. 388 * --------------------------------------------- 389 */ 390 mov x0, #DCCISW 391 bl dcsw_op_level1 392 393 /* --------------------------------------------- 394 * Come out of intra cluster coherency 395 * --------------------------------------------- 396 */ 397 bl cortex_a57_disable_smp 398 399 /* --------------------------------------------- 400 * Force the debug interfaces to be quiescent 401 * --------------------------------------------- 402 */ 403 mov x30, x18 404 b cortex_a57_disable_ext_debug 405endfunc cortex_a57_core_pwr_dwn 406 407 /* ------------------------------------------------------- 408 * The CPU Ops cluster power down function for Cortex-A57. 409 * ------------------------------------------------------- 410 */ 411func cortex_a57_cluster_pwr_dwn 412 mov x18, x30 413 414 /* --------------------------------------------- 415 * Turn off caches. 416 * --------------------------------------------- 417 */ 418 bl cortex_a57_disable_dcache 419 420 /* --------------------------------------------- 421 * Disable the L2 prefetches. 422 * --------------------------------------------- 423 */ 424 bl cortex_a57_disable_l2_prefetch 425 426#if !SKIP_A57_L1_FLUSH_PWR_DWN 427 /* ------------------------------------------------- 428 * Flush the L1 caches. 429 * ------------------------------------------------- 430 */ 431 mov x0, #DCCISW 432 bl dcsw_op_level1 433#endif 434 /* --------------------------------------------- 435 * Disable the optional ACP. 436 * --------------------------------------------- 437 */ 438 bl plat_disable_acp 439 440 /* ------------------------------------------------- 441 * Flush the L2 caches. 442 * ------------------------------------------------- 443 */ 444 mov x0, #DCCISW 445 bl dcsw_op_level2 446 447 /* --------------------------------------------- 448 * Come out of intra cluster coherency 449 * --------------------------------------------- 450 */ 451 bl cortex_a57_disable_smp 452 453 /* --------------------------------------------- 454 * Force the debug interfaces to be quiescent 455 * --------------------------------------------- 456 */ 457 mov x30, x18 458 b cortex_a57_disable_ext_debug 459endfunc cortex_a57_cluster_pwr_dwn 460 461#if REPORT_ERRATA 462/* 463 * Errata printing function for Cortex A57. Must follow AAPCS. 464 */ 465func cortex_a57_errata_report 466 stp x8, x30, [sp, #-16]! 467 468 bl cpu_get_rev_var 469 mov x8, x0 470 471 /* 472 * Report all errata. The revision-variant information is passed to 473 * checking functions of each errata. 474 */ 475 report_errata ERRATA_A57_806969, cortex_a57, 806969 476 report_errata ERRATA_A57_813419, cortex_a57, 813419 477 report_errata ERRATA_A57_813420, cortex_a57, 813420 478 report_errata A57_DISABLE_NON_TEMPORAL_HINT, cortex_a57, \ 479 disable_ldnp_overread 480 report_errata ERRATA_A57_826974, cortex_a57, 826974 481 report_errata ERRATA_A57_826977, cortex_a57, 826977 482 report_errata ERRATA_A57_828024, cortex_a57, 828024 483 report_errata ERRATA_A57_829520, cortex_a57, 829520 484 report_errata ERRATA_A57_833471, cortex_a57, 833471 485 486 ldp x8, x30, [sp], #16 487 ret 488endfunc cortex_a57_errata_report 489#endif 490 491 /* --------------------------------------------- 492 * This function provides cortex_a57 specific 493 * register information for crash reporting. 494 * It needs to return with x6 pointing to 495 * a list of register names in ascii and 496 * x8 - x15 having values of registers to be 497 * reported. 498 * --------------------------------------------- 499 */ 500.section .rodata.cortex_a57_regs, "aS" 501cortex_a57_regs: /* The ascii list of register names to be reported */ 502 .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", "" 503 504func cortex_a57_cpu_reg_dump 505 adr x6, cortex_a57_regs 506 mrs x8, CPUECTLR_EL1 507 mrs x9, CPUMERRSR_EL1 508 mrs x10, L2MERRSR_EL1 509 ret 510endfunc cortex_a57_cpu_reg_dump 511 512 513declare_cpu_ops cortex_a57, CORTEX_A57_MIDR, \ 514 cortex_a57_reset_func, \ 515 cortex_a57_core_pwr_dwn, \ 516 cortex_a57_cluster_pwr_dwn 517